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1. (WO2017137078) LEAKAGE COMPENSATION FOR A SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/137078 International Application No.: PCT/EP2016/052852
Publication Date: 17.08.2017 International Filing Date: 10.02.2016
IPC:
H03M 1/10 (2006.01) ,H03M 1/46 (2006.01) ,H03M 1/16 (2006.01)
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
M
CODING, DECODING OR CODE CONVERSION, IN GENERAL
1
Analogue/digital conversion; Digital/analogue conversion
10
Calibration or testing
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
M
CODING, DECODING OR CODE CONVERSION, IN GENERAL
1
Analogue/digital conversion; Digital/analogue conversion
12
Analogue/digital converters
34
Analogue value compared with reference values
38
sequentially only, e.g. successive approximation type
46
with digital/analogue converter for supplying reference values to converter
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
M
CODING, DECODING OR CODE CONVERSION, IN GENERAL
1
Analogue/digital conversion; Digital/analogue conversion
12
Analogue/digital converters
14
Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
16
with scale factor modification, i.e. by changing the amplification between the steps
Applicants:
TELEFONAKTIEBOLAGET LM ERICSSON (PUBL) [SE/SE]; S-164 83 Stockholm, SE
Inventors:
SUNDSTRÖM, Lars; SE
TILLMAN, Fredrik; SE
PALM, Mattias; SE
Agent:
ERICSSON; Torshamnsgatan 21-23 164 80 Stockholm, SE
Priority Data:
Title (EN) LEAKAGE COMPENSATION FOR A SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER
(FR) COMPENSATION DE FUITE POUR UN CONVERTISSEUR ANALOGIQUE-NUMÉRIQUE À APPROXIMATIONS SUCCESSIVES
Abstract:
(EN) An analog-to-digital conversion circuit (100) is disclosed. It comprises a switched- capacitor SAR- ADC, (110) arranged to receive an analog input signal (x(t)) and a clock signal, to sample the analog input signal (x(t)), and to generate a sequence (W(n)) of digital output words corresponding to samples of the analog input signal (x(t)), wherein the SAR- ADC (110) is arranged to generate a bit of the digital output word per cycle of the clock signal. It further comprises a clock-signal generator (120) arranged to supply the clock signal to the SAR- ADC (110), and a post-processing unit (140) adapted to receive the sequence (W(n)) of digital output words and generate a sequence of digital output numbers (y(n)), corresponding to the digital output words, based on bit weights assigned to the bits of the digital output words. The bit weights are selected to compensate for a decay of a signal internally in the SAR- ADC (110).
(FR) L'invention concerne un circuit de conversion analogique-numérique (100). Il comprend un condensateur commuté CAN SAR (110) agencé pour recevoir un signal d'entrée analogique (x(t)) et un signal d'horloge, échantillonner le signal d'entrée analogique (x(t)), et produire une séquence (W(n)) de mots de sortie numérique correspondant à des échantillons du signal d'entrée analogique (x(t)), où le CAN SAR (110) est agencé pour produire un bit du mot de sortie numérique par cycle de signal d'horloge. Il comprend aussi un générateur de signal d'horloge (120) agencé pour fournir le signal d'horloge au CAN SAR (110), et une unité de post-traitement (140) conçue pour recevoir la séquence (W(n)) de mots de sortie numérique et produire une séquence de nombres de sortie numérique (y(n)), correspondant aux mots de sortie numérique, en fonction de pondérations de bit attribuées aux bits des mots de sortie numérique. Les pondérations de bit sont sélectionnées pour compenser un affaiblissement interne d'un signal dans le CAN SAR (110).
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
EP3414841