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1. (WO2017136967) METHOD FOR MANUFACTURING ARRAY SUBSTRATE AND ARRAY SUBSTRATE
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/136967 International Application No.: PCT/CN2016/074791
Publication Date: 17.08.2017 International Filing Date: 29.02.2016
IPC:
H01L 21/77 (2017.01) ,H01L 27/02 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
Applicants:
武汉华星光电技术有限公司 WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD. [CN/CN]; 中国湖北省武汉市 东湖开发区高新大道666号生物城C5栋 Building C5, Biolake of Optics Valley, No. 666 Gaoxin Avenue, Wuhan East Lake High-tech Development Zone Wuhan, Hubei 430070, CN
Inventors:
邓思 DENG, Si; CN
Agent:
深圳市德力知识产权代理事务所 COMIPS INTELLECTUAL PROPERTY OFFICE; 中国广东省深圳市 福田区上步中路深勘大厦15E Room 15E, Shenkan Building, Shangbu Zhong Road, Futian District Shenzhen, Guangdong 518028, CN
Priority Data:
201610084686.614.02.2016CN
Title (EN) METHOD FOR MANUFACTURING ARRAY SUBSTRATE AND ARRAY SUBSTRATE
(FR) PROCÉDÉ DE FABRICATION DE SUBSTRAT DE RÉSEAU ET SUBSTRAT DE RÉSEAU
(ZH) 阵列基板的制作方法及阵列基板
Abstract:
(EN) Disclosed are a method for manufacturing an array substrate and an array substrate. The method adopts a protective passivation layer (90) made of an organic photoresist material instead of a conventional protective passivation layer (90) made of a silicon nitride material, and utilizes a single photomask to perform exposure and development processes on the protective passivation layer (90), and a planarization layer (70) so as to obtain a third via (91) above a first drain electrode (62) and a fourth via (92) above a second drain electrode (64). Compared with respective processes in the prior art, the method of the present invention allows reduction of both one photomask and one etching process, thereby simplifying the process flow and saving on production costs. The array substrate of the present invention has a simple structure, low manufacturing cost and good electrical properties.
(FR) La présente invention concerne un procédé de fabrication d'un substrat de réseau et un substrat de réseau. Le procédé adopte une couche de passivation protectrice (90) constituée d'un matériau de photoréserve organique au lieu d'une couche de passivation protectrice classique (90) constituée d'un matériau de nitrure de silicium, et utilise un photomasque unique pour effectuer des processus d'exposition et de développement sur la couche de passivation protectrice (90), et une couche de planarisation (70) de manière à obtenir un troisième trou de raccordement (91) au-dessus d'une première électrode de drain (62) et un quatrième trou de raccordement (92) au-dessus d'une seconde électrode de drain (64). Par rapport aux procédés respectifs de l'art antérieur, le procédé de la présente invention permet de réduire à la fois un photomasque et un processus de gravure, ce qui simplifie le déroulement des opérations et permet de réduire les coûts de production. Le substrat de réseau de la présente invention a une structure simple, un faible coût de fabrication et de bonnes propriétés électriques.
(ZH) 一种阵列基板的制作方法及阵列基板,该阵列基板的制作方法,通过采用由有机光阻材料制作的钝化保护层(90)来代替现有的氮化硅材料的钝化保护层(90),利用一道光罩对钝化保护层(90)和平坦层(70)进行曝光、显影处理,得到位于第一漏极(62)上方的第三过孔(91)、及位于第二漏极(64)上方的第四过孔(92),与现有技术的相应制程相比,既节省了一道光罩,又减少了一道蚀刻制程,从而达到简化工艺流程、以及节约生产成本的目的。阵列基板,结构简单,制作成本低,且具有良好的电学性能。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)
Also published as:
US20180047764