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1. (WO2017136577) SELF-ALIGNMENT OF METAL AND VIA USING SELECTIVE DEPOSITION
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/136577 International Application No.: PCT/US2017/016253
Publication Date: 10.08.2017 International Filing Date: 02.02.2017
IPC:
H01L 21/768 (2006.01) ,H01L 21/3205 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
768
Applying interconnections to be used for carrying current between separate components within a device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3205
Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers
Applicants:
TOKYO ELECTRON LIMITED [JP/JP]; Akasaka Biz Tower 3-1 Akasaka 5-chome Minato-ku, Tokyo 107-6325, JP
TOKYO ELECTRON U.S. HOLDINGS, INC. [US/US]; 2400 Grove Boulevard Austin, Texas 78741, US (JP)
Inventors:
SMITH, Jeffrey; US
DEVILLIERS, Anton J.; US
Agent:
MATHER, Joshua D.; US
Priority Data:
62/290,28202.02.2016US
Title (EN) SELF-ALIGNMENT OF METAL AND VIA USING SELECTIVE DEPOSITION
(FR) AUTO-ALIGNEMENT D'UN MÉTAL ET DE TROUS D'INTERCONNEXION À L'AIDE D'UN DÉPÔT SÉLECTIF
Abstract:
(EN) Techniques herein include methods of patterning substrates such as for back end of line (BEOL) metallization processes. Techniques herein enable fully self-aligned vias and lines. Processes herein include using selective deposition, protective films and combination etch masks for accurately patterning a substrate. In a substrate having uncovered portions of metal material and dielectric material, the dielectric material is grown upwardly without covering metal material. This raised dielectric material is conformally protected and used in subsequent patterning step to align via and line placement. Such combinations mitigate overlay errors.
(FR) La présente invention porte sur des techniques qui comprennent des procédés permettant de former des motifs sur des substrats telles que des procédés de métallisation d'unité de fabrication finale (BEOL pour Back End Of Line). Les techniques de l'invention permettent des trous d'interconnexion et des lignes complètement auto-alignés. Des procédés de l'invention consistent à utiliser un dépôt sélectif, des films protecteurs et une combinaison de masques de gravure pour former avec précision des motifs sur un substrat. Dans un substrat ayant des parties non couvertes d'un matériau métallique et d'un matériau diélectrique, le matériau diélectrique est tiré vers le haut sans recouvrir un matériau métallique. Ce matériau diélectrique en relief est protégé de manière conforme et utilisé ultérieurement au cours d'une étape de formation de motifs pour aligner un placement de trou d'interconnexion et de ligne. De telles combinaisons atténuent des erreurs de superposition.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
SG11201806578XKR1020180113200CN108780777