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1. (WO2017135132) SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/135132 International Application No.: PCT/JP2017/002652
Publication Date: 10.08.2017 International Filing Date: 26.01.2017
IPC:
H01L 21/822 (2006.01) ,H01L 21/3205 (2006.01) ,H01L 21/768 (2006.01) ,H01L 21/82 (2006.01) ,H01L 23/522 (2006.01) ,H01L 27/04 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3205
Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
768
Applying interconnections to be used for carrying current between separate components within a device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
522
including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
Applicants:
学校法人慶應義塾 KEIO UNIVERSITY [JP/JP]; 東京都港区三田二丁目15番45号 15-45, Mita 2-chome, Minato-ku, Tokyo 1088345, JP
Inventors:
黒田 忠広 KURODA, Tadahiro; JP
Agent:
土井 健二 DOI, Kenji; JP
林 恒徳 HAYASHI, Tsunenori; JP
眞鍋 潔 MANABE, Kiyoshi; JP
Priority Data:
2016-01881703.02.2016JP
Title (EN) SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
(FR) DISPOSITIF DE CIRCUIT INTÉGRÉ À SEMI-CONDUCTEUR
(JA) 半導体集積回路装置
Abstract:
(EN) A semiconductor integrated circuit device in which inductive coupling between coils is improved and supply voltage drops in power supply wires are suppressed as a result of devising a power supply network. The semiconductor integrated circuit device is provided with a power supply network equipped with a first power supply wiring group that passes through the X direction and a second power supply wiring group that passes through the Y direction when viewing the interiors of all of the coils of a first coil array, which is formed in the same horizontal position in a multilayer wiring structure provided on a substrate and comprises a plurality of coils positioned at prescribed intervals, from the lamination direction of the multilayer wiring structure. A closed circuit that surrounds the sides of a coil is formed by at least part of the first power supply wiring group and at least part of the second power supply wiring group.
(FR) L'invention porte sur un dispositif de circuit intégré à semi-conducteur dans lequel un couplage inductif entre des bobines est amélioré et des chutes de tension d'alimentation dans des fils d'alimentation électrique sont supprimées en conséquence de la conception d'un réseau d'alimentation électrique. Le dispositif de circuit intégré à semi-conducteur est pourvu d'un réseau d'alimentation électrique équipé d'un premier groupe de câblage d'alimentation électrique qui passe par la direction X et d'un second groupe de câblage d'alimentation qui passe par la direction Y quand on regarde l'intérieur de toutes les bobines d'un premier groupement de bobines, qui est formé dans la même position horizontale dans une structure de câblage multicouche disposée sur un substrat et comprend une pluralité de bobines positionnées à intervalles prescrits, dans la direction de stratification de la structure de câblage multicouche. Un circuit fermé qui entoure les côtés d'une bobine est formé par au moins une partie du premier groupe de câblage d'alimentation électrique et au moins une partie du second groupe de câblage d'alimentation électrique.
(JA) 半導体集積回路装置に関し、電源網を工夫することによって、コイル間の誘導結合度の改善と電源線における電源電圧降下の抑制を両立する。基板上に設けた多層配線構造における同一の水平位置に形成され、所定の間隔で配置された複数のコイルからなる第1のコイルアレイの全てのコイル内部を前記多層配線構造の積層方向から見てX方向を通過する第1の電源配線群と、Y方向を通過する第2の電源配線群を備えた電源網を設け、前記第1の電源配線群の少なくとも一部と前記第2の電源配線群の少なくとも一部により、前記コイルの周辺を囲む閉回路を形成する。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)
Also published as:
KR1020180109906US20190051720