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1. (WO2017135111) CIRCUIT SUBSTRATE AND METHOD FOR PRODUCING CIRCUIT SUBSTRATE
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/135111 International Application No.: PCT/JP2017/002396
Publication Date: 10.08.2017 International Filing Date: 24.01.2017
IPC:
H05K 3/46 (2006.01) ,H01L 23/12 (2006.01) ,H05K 1/16 (2006.01)
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3
Apparatus or processes for manufacturing printed circuits
46
Manufacturing multi-layer circuits
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
12
Mountings, e.g. non-detachable insulating substrates
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1
Printed circuits
16
incorporating printed electric components, e.g. printed resistor, capacitor, inductor
Applicants:
富士ゼロックス株式会社 FUJI XEROX CO., LTD. [JP/JP]; 東京都港区赤坂九丁目7番3号 7-3, Akasaka 9-chome, Minato-ku, Tokyo 1070052, JP
株式会社野田スクリーン NODA SCREEN CO., LTD. [JP/JP]; 愛知県小牧市大字本庄字大坪415番地 415, Aza-Otsubo, Oaza-Honjo, Komaki-shi, Aichi 4850821, JP
Inventors:
井口 大介 IGUCHI Daisuke; JP
服部 篤典 HATTORI Atsunori; JP
Agent:
特許業務法人航栄特許事務所 KOH-EI PATENT FIRM, P.C.; 東京都港区西新橋一丁目7番13号 虎ノ門イーストビルディング9階 Toranomon East Bldg. 9F, 7-13, Nishi-Shimbashi 1-chome, Minato-ku, Tokyo 1050003, JP
高松 猛 TAKAMATSU Takeshi; JP
Priority Data:
2016-01917003.02.2016JP
Title (EN) CIRCUIT SUBSTRATE AND METHOD FOR PRODUCING CIRCUIT SUBSTRATE
(FR) SUBSTRAT DE CIRCUIT ET PROCÉDÉ DE FABRICATION DE SUBSTRAT DE CIRCUIT
(JA) 回路基板および回路基板の製造方法
Abstract:
(EN) This circuit substrate is provided with a base material and a capacitor layer having: a first metal layer disposed on the base material; and a dielectric layer disposed on the first metal layer; and a second metal layer disposed on the dielectric layer. The first metal layer has a first electrode region which is connected to a first terminal of a capacitor element that is disposed on the base material and that supplies an electric current to a circuit component via the capacitor layer, and which is exposed from the dielectric layer. The second metal layer has a second electrode region which is connected to a second terminal of the capacitor element, and in which the second metal layer is exposed.
(FR) L'invention concerne un substrat de circuit qui comprend un matériau de base et une couche de condensateur comprenant : une première couche métallique disposée sur le matériau de base ; une couche diélectrique disposée sur la première couche métallique ; et une seconde couche métallique disposée sur la couche diélectrique. La première couche métallique comprend une première région d'électrode qui est connectée à une première borne d'un élément de condensateur qui est disposé sur le matériau de base et qui fournit un courant électrique à un composant de circuit par l'intermédiaire de la couche de condensateur, et qui est mise à nu de la couche diélectrique. La seconde couche métallique comprend une seconde région d'électrode qui est connectée à une seconde borne de l'élément de condensateur, et dans laquelle la seconde couche métallique est mise à nu.
(JA) 回路基板は、基材と、前記基材上に設けられた第1の金属層と、当該第1の金属層上に設けられた誘電体層と、当該誘電体層上に設けられた第2の金属層とを有するキャパシタ層と、を備える。前記第1の金属層は、前記基材上に設けられ前記キャパシタ層を介して回路部品に電流を供給するキャパシタ素子の第1の端子が接続される、前記誘電体層から露出した第1の電極領域を有し、前記第2の金属層は、前記キャパシタ素子の第2の端子が接続される、当該第2の金属層が露出した第2の電極領域を有する。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)
Also published as:
US20170221848CN108293304US20180294240