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1. (WO2017135061) SEMICONDUCTOR INTEGRATED CIRCUIT AND SIGNAL PROCESSING METHOD
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/135061 International Application No.: PCT/JP2017/001851
Publication Date: 10.08.2017 International Filing Date: 20.01.2017
IPC:
G01R 31/28 (2006.01) ,G01R 27/26 (2006.01) ,H01L 21/66 (2006.01)
G PHYSICS
01
MEASURING; TESTING
R
MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31
Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
28
Testing of electronic circuits, e.g. by signal tracer
G PHYSICS
01
MEASURING; TESTING
R
MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
27
Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
02
Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
26
Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
66
Testing or measuring during manufacture or treatment
Applicants:
ソニー株式会社 SONY CORPORATION [JP/JP]; 東京都港区港南1丁目7番1号 1-7-1, Konan, Minato-ku, Tokyo 1080075, JP
Inventors:
森 茂貴 MORI Shigetaka; JP
Agent:
西川 孝 NISHIKAWA Takashi; JP
稲本 義雄 INAMOTO Yoshio; JP
Priority Data:
2016-01754101.02.2016JP
Title (EN) SEMICONDUCTOR INTEGRATED CIRCUIT AND SIGNAL PROCESSING METHOD
(FR) CIRCUIT INTÉGRÉ SEMI-CONDUCTEUR ET PROCÉDÉ DE TRAITEMENT DE SIGNAUX
(JA) 半導体集積回路および信号処理方法
Abstract:
(EN) The present disclosure relates to a semiconductor integrated circuit and a signal processing method which make it possible to improve measuring accuracy. Pulses for which pulse generation and disconnection are controlled by a control circuit are supplied to a pulse distribution circuit and a CP circuit. The pulse distribution circuit distributes, from one pulse, two or more pulses that do not overlap one another, and supplies the two or more pulses to a CBCM circuit. The CBCM circuit is configured by connecting a capacitive element, serving as an object to be measured, to the output of a measurement core circuit known as a pseudo inverter. In the CP circuit, a pulse configured such that the channel of a non-measured MISFET transitions from an accumulation state to an inversion state is input into a gate electrode, and a CP current flowing via a trap acting around a recombination of a gate insulating film and a semiconductor substrate interface is monitored from the substrate side. The present disclosure can be applied, for example, to semiconductor integrated circuits for evaluating characteristics of a gate insulating film of a MISFET.
(FR) La présente invention porte sur un circuit intégré semi-conducteur et sur un procédé de traitement de signaux qui permettent d’améliorer la précision de mesure. Des impulsions pour lesquelles la génération d’impulsion et la déconnexion sont commandées par un circuit de commande sont transmises à un circuit de distribution d’impulsions et à un circuit CP. Le circuit de distribution d’impulsions distribue, à partir d’une impulsion, deux impulsions ou plus qui ne se superposent pas, et transmet les deux impulsions ou plus à un circuit CBCM. Le circuit CBCM est conçu en connectant un élément capacitif, servant d’objet à mesurer, à la sortie d’un circuit noyau de mesure connu comme pseudo-onduleur. Dans le circuit CP, une impulsion conçue de sorte que le canal d’un MISFET non mesuré passe d’un état d’accumulation à un état d’inversion est entrée dans une électrode de grille, et un courant de CP circulant par un piège agissant autour d’une recombinaison d’une pellicule isolante de grille et d’une interface de substrat semi-conducteur est contrôlé depuis le côté du substrat. La présente invention peut être appliquée, par exemple, à des circuits intégrés semi-conducteurs pour l’évaluation de caractéristiques d’une pellicule isolante de grille d’un MISFET.
(JA) 本開示は、測定精度を向上させることができるようにする半導体集積回路および信号処理方法に関する。 制御回路によりパルス生成および切断が制御されたパルスは、パルス分配回路とCP回路に供給される。パルス分配回路は、1つのパルスから、互いにオーバーラップしない2以上のパルスに分配して、CBCM回路に供給する。CBCM回路は、擬似インバータと呼ばれる測定コア回路の出力に、測定対象となる容量素子が接続されて、構成されている。CP回路は、非測定MISFETのチャネルが蓄積状態から反転状態へと遷移するようなパルスをゲート電極に入力し、ゲート絶縁膜と半導体基板界面の再結合を中心として働くトラップを介して流れるCP電流を基板側からモニタする。本開示は、例えば、MISFETのゲート絶縁膜の特性を評価する半導体集積回路に適用することができる。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)
Also published as:
US20190049498