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1. (WO2017134919) SINGLE-SIDE POLISHING METHOD FOR SILICON WAFER
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/134919 International Application No.: PCT/JP2016/085929
Publication Date: 10.08.2017 International Filing Date: 02.12.2016
IPC:
H01L 21/304 (2006.01) ,B24B 37/10 (2012.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
302
to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
304
Mechanical treatment, e.g. grinding, polishing, cutting
B PERFORMING OPERATIONS; TRANSPORTING
24
GRINDING; POLISHING
B
MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
37
Lapping machines or devices; Accessories
04
designed for working plane surfaces
07
characterised by the movement of the work or lapping tool
10
for single side lapping
Applicants:
株式会社SUMCO SUMCO CORPORATION [JP/JP]; 東京都港区芝浦一丁目2番1号 2-1, Shibaura 1-chome, Minato-ku Tokyo 1058634, JP
Inventors:
中島 敏治 NAKAJIMA Toshiharu; JP
小佐々 和明 KOZASA Kazuaki; JP
杉森 勝久 SUGIMORI Katsuhisa; JP
小淵 俊也 KOBUCHI Syunya; JP
Agent:
杉村 憲司 SUGIMURA Kenji; JP
Priority Data:
2016-01875903.02.2016JP
Title (EN) SINGLE-SIDE POLISHING METHOD FOR SILICON WAFER
(FR) PROCÉDÉ DE POLISSAGE SIMPLE FACE D'UNE TRANCHE DE SILICIUM
(JA) シリコンウェーハの片面研磨方法
Abstract:
(EN) The purpose of the present invention is to provide a single-side polishing method for a silicon wafer capable of significantly improving the generation rate of minute step defects. The single-side polishing method for a silicon wafer according to the present invention includes: a first polishing step for performing the polishing of a single side of the silicon wafer based on a first polishing condition; and after the first polishing step, a second polishing step for performing the polishing of the silicon wafer based on a second polishing condition that has changed at least either of a pressurizing force and the relative speed in the first polishing condition, and is characterized in that the polishing rate ratio based on the first polishing condition is greater than the polishing rate ratio based on the second polishing condition.
(FR) La présente invention a pour objet de fournir un procédé de polissage simple face d'une tranche de silicium, permettant d'améliorer considérablement le taux de génération de minuscules défauts en forme de marche. Le procédé de polissage simple face d'une tranche de silicium selon la présente invention comprend : une première étape de polissage qui consiste à effectuer le polissage d'une seule face de la tranche de silicium sur la base de premières conditions de polissage ; après la première étape de polissage, une seconde étape de polissage qui consiste à effectuer le polissage de la tranche de silicium sur la base de secondes conditions de polissage dans lesquelles la force de pression et/ou la vitesse relative sont modifiées par rapport aux premières conditions de polissage, ledit procédé de polissage étant caractérisé en ce que le rapport de vitesse de polissage sur la base des premières conditions de polissage est supérieur au rapport de vitesse de polissage sur la base des secondes conditions de polissage.
(JA) 段差状微小欠陥の発生率を大幅に改善することのできるシリコンウェーハの片面研磨方法を提供することを目的とする。 本発明によるシリコンウェーハの片面研磨方法は、第1研磨条件により前記シリコンウェーハの前記片面の研磨を行う第1研磨工程と、該第1研磨工程の後、前記第1研磨条件における加圧力および前記相対速度の少なくともいずれかを変化させた第2研磨条件により、前記シリコンウェーハの研磨を行う第2研磨工程と、を含み、前記第1研磨条件による研磨レート比が、前記第2研磨条件による研磨レート比よりも大きいことを特徴とする。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, KE, KG, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)
Also published as:
KR1020180075668DE112016006354CN108885982US20190030676