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1. (WO2017134761) CAPACITOR-INCORPORATED MULTILAYER WIRING BOARD AND METHOD FOR MANUFACTURING SAME
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/134761 International Application No.: PCT/JP2016/053155
Publication Date: 10.08.2017 International Filing Date: 03.02.2016
IPC:
H05K 1/16 (2006.01) ,H01G 4/12 (2006.01) ,H05K 3/46 (2006.01)
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1
Printed circuits
16
incorporating printed electric components, e.g. printed resistor, capacitor, inductor
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
G
CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
4
Fixed capacitors; Processes of their manufacture
002
Details
018
Dielectrics
06
Solid dielectrics
08
Inorganic dielectrics
12
Ceramic dielectrics
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3
Apparatus or processes for manufacturing printed circuits
46
Manufacturing multi-layer circuits
Applicants:
富士通株式会社 FUJITSU LIMITED [JP/JP]; 神奈川県川崎市中原区上小田中4丁目1番1号 1-1, Kamikodanaka 4-chome, Nakahara-ku, Kawasaki-shi, Kanagawa 2118588, JP
Inventors:
赤星知幸 AKAHOSHI Tomoyuki; JP
水谷大輔 MIZUTANI Daisuke; JP
Agent:
土井健二 DOI Kenji; JP
Priority Data:
Title (EN) CAPACITOR-INCORPORATED MULTILAYER WIRING BOARD AND METHOD FOR MANUFACTURING SAME
(FR) CARTE DE CÂBLAGE MULTICOUCHE À CONDENSATEUR INCORPORÉ ET SON PROCÉDÉ DE FABRICATION
(JA) キャパシタ内蔵多層配線基板及びその製造方法
Abstract:
(EN) In a capacitor-incorporated multilayer wiring board and a method for manufacturing the capacitor-incorporated multilayer wiring board, in order to reduce signal transmission deterioration due to parasitic capacity of a capacitor dielectric film without damaging a substrate, the capacitor dielectric film is removed from a region close to a signal line via, said region being provided with a lower layer conductor pattern, and a through opening is formed.
(FR) Selon la présente invention, dans une carte de câblage multicouche à condensateur incorporé et un procédé de fabrication de la carte de câblage multicouche à condensateur incorporé, afin de réduire la détérioration de transmission de signaux due à la capacité parasite d'un film diélectrique de condensateur sans endommager un substrat, le film diélectrique de condensateur est retiré d'une zone proche d'un trou d'interconnexion de ligne de signal, ladite zone étant pourvue d'un motif conducteur de couche inférieure, et une ouverture traversante est formée.
(JA) キャパシタ内蔵多層配線基板及びその製造方法に関し、基板にダメージを与えることなく、キャパシタ誘電体膜の寄生容量による信号伝送の劣化を低減するために、信号線用ビアの近傍の下層導体パターンを設けた領域においてキャパシタ誘電体膜を除去して貫通開口部を形成する。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)