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1. (WO2017133284) CONTROL CIRCUIT FOR CONTROLLING A NOISE REDUCTION THIN FILM TRANSISTOR IN A SHIFT REGISTER UNIT AND METHOD OF REDUCING NOISE
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/133284 International Application No.: PCT/CN2016/104692
Publication Date: 10.08.2017 International Filing Date: 04.11.2016
IPC:
G09G 3/20 (2006.01)
G PHYSICS
09
EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
G
ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
3
Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
20
for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
Applicants:
BOE TECHNOLOGY GROUP CO., LTD. [CN/CN]; No.10 Jiuxianqiao Rd., Chaoyang District Beijing 100015, CN
Inventors:
SHANG, Guangliang; CN
HAN, Seungwoo; CN
HAN, Mingfu; CN
ZHENG, Haoliang; CN
YAO, Xing; CN
CHOI, Hyunsic; CN
Agent:
TEE&HOWE INTELLECTUAL PROPERTY ATTORNEYS; CHEN, Yuan 10th Floor, Tower D, Minsheng Financial Center 28 Jianguomennei Avenue, Dongcheng District Beijing 100005, CN
Priority Data:
201610076597.703.02.2016CN
Title (EN) CONTROL CIRCUIT FOR CONTROLLING A NOISE REDUCTION THIN FILM TRANSISTOR IN A SHIFT REGISTER UNIT AND METHOD OF REDUCING NOISE
(FR) CIRCUIT DE COMMANDE PERMETTANT DE COMMANDER UN TRANSISTOR EN COUCHES MINCES DE RÉDUCTION DE BRUIT DANS UNE UNITÉ DE REGISTRE À DÉCALAGE ET PROCÉDÉ DE RÉDUCTION DU BRUIT
Abstract:
(EN) A control circuit (30) for controlling a noise reduction thin film transistor in a shift register unit (40). The control circuit (30) includes a timer (31) for initiating a timing process when the shift register (40) is turned on, to obtain an operating time of the shift register (40); a threshold voltage calculator (32) coupled to the timer (31) for calculating a present threshold voltage based on the operating time, a gate voltage of the noise reduction thin film transistor, and an initial threshold voltage of the noise reduction thin film transistor; and a gate voltage controller (33) coupled to the threshold voltage calculator (32) for adjusting the gate voltage of the noise reduction thin film transistor during the noise reduction phase, to control the noise reduction thin film transistor in an ON state during the noise reduction phase.
(FR) L'invention concerne un circuit de commande (30) permettant de commander un transistor en couches minces de réduction de bruit dans une unité de registre à décalage (40). Le circuit de commande (30) comprend un temporisateur (31) destiné à déclencher un processus de synchronisation lorsque le registre à décalage (40) est activé, pour obtenir une durée de fonctionnement du registre à décalage (40); un calculateur de tension de seuil (32) couplé au temporisateur (31) pour calculer une tension de seuil actuelle en se basant sur la durée de fonctionnement, une tension de grille du transistor en couches minces de réduction de bruit, et une tension de seuil initiale du transistor en couches minces de réduction de bruit; et un dispositif de commande de tension de grille (33) couplé au calculateur de tension de seuil (32) pour ajuster la tension de grille du transistor en couches minces de réduction de bruit pendant la phase de réduction de bruit, pour commander le transistor en couches minces de réduction du bruit dans un état activé pendant la phase de réduction de bruit.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
US20180301200EP3411870