Search International and National Patent Collections
Some content of this application is unavailable at the moment.
If this situation persists, please contact us atFeedback&Contact
1. (WO2017133111) MANUFACTURING METHOD FOR THIN-FILM TRANSISTOR, MANUFACTURING METHOD FOR ARRAY SUBSTRATE, ARRAY SUBSTRATE AND DISPLAY APPARATUS
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/133111 International Application No.: PCT/CN2016/081424
Publication Date: 10.08.2017 International Filing Date: 09.05.2016
IPC:
H01L 21/336 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
Applicants:
京东方科技集团股份有限公司 BOE TECHNOLOGY GROUP CO., LTD. [CN/CN]; 中国北京市 朝阳区酒仙桥路10号 No.10 Jiuxianqiao Rd., Chaoyang District Beijing 100015, CN
北京京东方光电科技有限公司 BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD. [CN/CN]; 中国北京市 经济技术开发区西环中路8号 No.8 Xihuanzhonglu, BDA Beijing 100176, CN
Inventors:
林子锦 LIN, Zijin; CN
赵海生 ZHAO, Haisheng; CN
裴晓光 PEI, Xiaoguang; CN
彭志龙 PENG, Zhilong; CN
孙东江 SUN, Dongjiang; CN
Agent:
北京银龙知识产权代理有限公司 DRAGON INTELLECTUAL PROPERTY LAW FIRM; 中国北京市 海淀区西直门北大街32号院枫蓝国际中心2号楼10层 10F, Bldg. 2, Maples International Center No. 32 Xizhimen North Street, Haidian District Beijing 100082, CN
Priority Data:
201610073355.202.02.2016CN
Title (EN) MANUFACTURING METHOD FOR THIN-FILM TRANSISTOR, MANUFACTURING METHOD FOR ARRAY SUBSTRATE, ARRAY SUBSTRATE AND DISPLAY APPARATUS
(FR) PROCÉDÉ DE FABRICATION DE TRANSISTOR EN COUCHES MINCES, PROCÉDÉ DE FABRICATION DE SUBSTRAT DE MATRICE, SUBSTRAT DE MATRICE ET APPAREIL D'AFFICHAGE
(ZH) 薄膜晶体管的制作方法,阵列基板的制作方法、阵列基板、显示装置
Abstract:
(EN) Disclosed are a manufacturing method for a thin-film transistor and an array substrate, an array substrate and a display apparatus. The manufacturing method for the thin-film transistor comprises: forming a transition layer (10) on a substrate (1); patterning the transition layer (10) to form a transition layer reserved area and a transition layer unreserved area, the transition unreserved area corresponds to a pattern of a first structural layer (4); forming, on the substrate (1) having the pattern of the transition layer (10), a material layer for forming the first structural layer (4); and removing the transition layer (10) such that a part, remaining on the substrate (1), of the material layer forms a pattern of the first structural layer (4).
(FR) La présente invention concerne un procédé de fabrication d'un transistor en couches minces et d'un substrat de réseau, un substrat de réseau et un appareil d'affichage. Le procédé de fabrication de transistor en couches minces consiste à : former une couche de transition (10) sur un substrat (1); modeler la couche de transition (10) afin de former une zone réservée de couche de transition et une zone non réservée de couche de transition, ladite zone non réservée de transition correspondant à un motif d'une première couche structurelle (4); former, sur le substrat (1) portant le motif de la couche de transition (10), une couche de matériau destinée à former la première couche structurelle (4); et retirer la couche de transition (10) de sorte qu'une partie de la couche de matériau qui reste sur le substrat (1) forme un motif de la première couche structurelle (4).
(ZH) 一种薄膜晶体管及阵列基板的制作方法、阵列基板、显示装置。其中,薄膜晶体管的制作方法包括:在基板(1)上形成过渡层(10);对所述过渡层(10)进行构图形成过渡层保留区域和过渡层未保留区域,所述过渡层未保留区域对应第一结构层(4)的图形;在形成有所述过渡层(10)的图形的基板(1)上形成用于形成所述第一结构层(4)的材料层;除去所述过渡层(10),所述材料层留在基板(1)上的部分形成所述第一结构层(4)的图形。
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)
Also published as:
US20180331131