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1. (WO2017133002) FIELD EFFECT TRANSISTOR AND PREPARATION METHOD FOR FIELD EFFECT TRANSISTOR
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/133002 International Application No.: PCT/CN2016/073680
Publication Date: 10.08.2017 International Filing Date: 05.02.2016
IPC:
H01L 27/108 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
105
including field-effect components
108
Dynamic random access memory structures
Applicants:
华为技术有限公司 HUAWEI TECHNOLOGIES CO., LTD. [CN/CN]; 中国广东省深圳市 龙岗区坂田华为总部办公楼 Huawei Administration Building, Bantian,Longgang District Shenzhen, Guangdong 518129, CN
Inventors:
徐慧龙 XU, Huilong; CN
秦旭东 QIN, Xudong; CN
张臣雄 ZHANG, Chen-Xiong; CN
Agent:
广州三环专利商标代理有限公司 SCIHEAD IP LAW FIRM; 中国广东省广州市 越秀区先烈中路80号汇华商贸大厦1508室 Room 1508, Huihua Commercial & Trade Building No. 80, XianLie Zhong Road,Yuexiu District Guangzhou, Guangdong 510070, CN
Priority Data:
Title (EN) FIELD EFFECT TRANSISTOR AND PREPARATION METHOD FOR FIELD EFFECT TRANSISTOR
(FR) TRANSISTOR À EFFET DE CHAMP ET PROCÉDÉ DE PRÉPARATION DE TRANSISTOR À EFFET DE CHAMP
(ZH) 场效应晶体管及场效应晶体管的制备方法
Abstract:
(EN) Provided are a field effect transistor (10) and a preparation method for a field effect transistor. The field effect transistor comprises a substrate (110), wherein the substrate comprises a first surface (110a); a gate electrode (120), wherein the gate electrode is embedded in the substrate from the first surface, and one end face of the gate electrode is flush with the first surface; a gate dielectric layer (130) covering the first surface and the end face, flush with the first surface, of the gate electrode; a graphene layer (140) arranged on a surface, facing away from the substrate, of the gate dielectric layer; a source electrode (150) arranged on a surface, facing away from the gate dielectric layer, of the graphene layer; and a drain electrode (160) arranged on the surface, facing away from the gate dielectric layer, of the graphene layer, wherein there is a gap between same and the source electrode.
(FR) L'invention concerne un transistor à effet de champ (10) et un procédé de préparation d'un transistor à effet de champ. Le transistor à effet de champ comprend un substrat (110), le substrat comprend une première surface (110a); une électrode de grille (120), l'électrode de grille étant incorporée dans le substrat depuis la première surface, et une face d'extrémité de l'électrode de grille affleurant à la première surface; une couche diélectrique de grille (130) recouvrant la première surface et la face d'extrémité, affleurant à la première surface, de l'électrode de grille; une couche de graphène (140) agencée sur une surface, tournant le dos au substrat, de la couche diélectrique de grille; une électrode de source (150) agencée sur une surface, tournant le dos à la couche diélectrique de grille, de la couche de graphène; et une électrode de drain (160), agencée sur la surface, tournant le dos à la couche diélectrique de grille, de la couche de graphène, un espace existant entre cette dernière et l'électrode de source.
(ZH) 提供一种场效应晶体管(10)及场效应晶体管的制备方法。场效应晶体管包括衬底(110),衬底包括第一表面(110a);栅极(120),栅极自第一表面嵌设于衬底,且栅极的一端面与第一表面平齐;栅介质层(130),覆盖第一表面及栅极与第一表面平齐的端面;石墨烯层(140),设置在栅介质层背离衬底的表面;源极(150),设置在石墨烯层背离栅介质层的表面;及漏极(160),设置在石墨烯层背离栅介质层的表面,且与源极之间设有间隙。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)
Also published as:
CN108475680