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1. (WO2017132462) SEMICONDUCTOR PACKAGING STRUCTURE AND PACKAGE HAVING STRESS RELEASE STRUCTURE
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/132462 International Application No.: PCT/US2017/015261
Publication Date: 03.08.2017 International Filing Date: 27.01.2017
IPC:
H01L 23/367 (2006.01) ,H01L 23/373 (2006.01) ,H01L 23/06 (2006.01) ,H01L 23/482 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
34
Arrangements for cooling, heating, ventilating or temperature compensation
36
Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks
367
Cooling facilitated by shape of device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
34
Arrangements for cooling, heating, ventilating or temperature compensation
36
Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks
373
Cooling facilitated by selection of materials for the device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
02
Containers; Seals
06
characterised by the material of the container or its electrical properties
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
482
consisting of lead-in layers inseparably applied to the semiconductor body
Applicants:
KYOCERA INTERNATIONAL, INC. [US/US]; 8611 Balboa Ave. San Diego, CA 92123-1501, US
Inventors:
TOMIE, Satoru; US
EBLEN, Mark; US
WATANABE, Eiji; US
TANAKA, Eiji; US
Agent:
CONNELL, Kathleen, L.; US
Priority Data:
62/288,03428.01.2016US
Title (EN) SEMICONDUCTOR PACKAGING STRUCTURE AND PACKAGE HAVING STRESS RELEASE STRUCTURE
(FR) STRUCTURE D'ENCAPSULATION DE SEMI-CONDUCTEURS ET BOÎTIER PRÉSENTANT UNE STRUCTURE DE DÉTENTE DES CONTRAINTES
Abstract:
(EN) A semiconductor packaging structure includes a copper heat-sink with a shim projection which provides a stress release structure. The heat-sink with the shim projection may be used in conjunction with a pedestal in order to further reduce the thermal stress produced from the mismatch of thermal properties between the copper heat-sink metal and the ceramic frame. The copper heat-sink with a shim projection may also be part of the semiconductor package along with a lead frame, the ceramic frame, a semiconductor device, a capacitor, a wire bond and a ceramic lid or an encapsulation. The copper heat-sink, the ceramic frame and the lead frame are all chosen to be cost effective, and chosen such that the packaging process for the semiconductor device is able to achieve a smaller size while maintaining high reliability, low cost, and suitability for volume manufacturing.
(FR) Cette invention concerne une structure d'encapsulation de semi-conducteurs, comprenant un dissipateur de chaleur en cuivre avec une saillie en forme de cale qui forme une structure de détente des contraintes. Le dissipateur thermique avec la saillie en forme de cale peut être utilisé conjointement avec un socle afin de réduire les contraintes thermiques issues de la disparité des propriétés thermiques entre le métal du dissipateur de chaleur en cuivre et le cadre céramique. Le dissipateur de chaleur en cuivre avec une saillie en forme de cale peut également faire partie du boîtier de semi-conducteurs avec une grille de connexion, le cadre céramique, un dispositif à semi-conducteur, un condensateur, une soudure de fils et un couvercle céramique ou une encapsulation. Le dissipateur de chaleur en cuivre, le cadre céramique et la grille de connexion sont tous choisis de sorte à être rentables, et choisis de telle sorte que le processus d'encapsulation pour le dispositif à semi-conducteur permette d'obtenir un encombrement moindre tout en maintenant une haute fiabilité, un coût réduit et l'aptitude à la production de masse.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)