Search International and National Patent Collections
Some content of this application is unavailable at the moment.
If this situation persists, please contact us atFeedback&Contact
1. (WO2017131981) ENHANCED PARALLEL PROTECTION CIRCUIT
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/131981 International Application No.: PCT/US2017/013622
Publication Date: 03.08.2017 International Filing Date: 16.01.2017
IPC:
H02H 3/05 (2006.01) ,H01M 10/00 (2006.01) ,H02H 7/18 (2006.01)
H ELECTRICITY
02
GENERATION, CONVERSION, OR DISTRIBUTION OF ELECTRIC POWER
H
EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
3
Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection
02
Details
05
with means for increasing reliability, e.g. redundancy arrangements
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
M
PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
10
Secondary cells; Manufacture thereof
H ELECTRICITY
02
GENERATION, CONVERSION, OR DISTRIBUTION OF ELECTRIC POWER
H
EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
7
Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
18
for batteries; for accumulators
Applicants:
MICROSOFT TECHNOLOGY LICENSING, LLC [US/US]; Attn: Patent Group Docketing (Bldg. 8/1000) One Microsoft Way Redmond, Washington 98052-6399, US
Inventors:
DUTRA, Jonathan Alan; US
FULLAM, Scott Francis; US
MEHTA, Agustya Ruchir; US
PENNY, Junius Mark; US
LUKOFSKY, David; US
Agent:
MINHAS, Sandip; US
CHEN, Wei-Chen Nicholas; US
DRAKOS, Katherine J.; US
KADOURA, Judy M.; US
HOLMES, Danielle J.; US
SWAIN, Cassandra T.; US
WONG, Thomas S.; US
CHOI, Daniel; US
Priority Data:
15/007,17126.01.2016US
Title (EN) ENHANCED PARALLEL PROTECTION CIRCUIT
(FR) CIRCUIT DE PROTECTION PARALLÈLE AMÉLIORÉ
Abstract:
(EN) A system (100) using separate battery packs (102A, 102B) in a parallel configuration is arranged with multiple protection circuit modules (PCMs). The PCMs (111) are configured to detect fault conditions, such as over voltage, under voltage, excess current, excess heat, etc. Individual PCMs can be configured to control associated switches (103A, 103B) and/or other components. When a fault condition is detected by an individual PCM, the individual PCM triggers one or more associated switches to shut down one or more components. In addition, by the use of the techniques disclosed herein, the individual PCM can also trigger switches that are controlled by other PCMs. Configurations disclosed herein mitigate occurrences where a multi-PCM device is operating after at least one PCM has shut down. Configurations disclosed herein provide safeguards and redundant protection in scenarios where a fault event is detected by one PCM and not detected by another PCM in a parallel configuration.
(FR) Selon l'invention, un système (100) utilisant des blocs-batteries séparés (102A, 102B) en configuration parallèle est doté de multiples modules de circuit de protection (PCM). Les PCM (111) sont configurés pour détecter des conditions de défaut, telles qu'une surtension, une sous-tension, une surintensité, une chaleur excessive, etc. Des PCM individuels peuvent être configurés pour commander des interrupteurs associés (103A, 103B) et/ou d'autres composants. Lorsqu'une condition de défaut est détectée par un PCM individuel, le PCM individuel déclenche un ou plusieurs interrupteurs associés pour mettre hors tension un ou plusieurs composants. De plus, par utilisation des techniques de l'invention, le PCM individuel peut également déclencher des interrupteurs qui sont commandés par d'autres PCM. Des configurations de l'invention atténuent des occurrences où un dispositif à multiples PCM est en fonctionnement après qu'au moins un PCM a effectué une mise hors tension. Des configurations de l'invention offrent des sauvegardes et une protection redondante dans des scénarios où un événement de défaut est détecté par un PCM et non détecté par un autre PCM en configuration parallèle.
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
CN108370150EP3408908