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1. (WO2017131941) MEMORY CELL SCREEN FOR BTI EFFECT
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/131941 International Application No.: PCT/US2017/012710
Publication Date: 03.08.2017 International Filing Date: 09.01.2017
Chapter 2 Demand Filed: 06.07.2017
IPC:
G11C 5/14 (2006.01) ,G11C 8/08 (2006.01) ,G11C 11/417 (2006.01) ,G11C 11/418 (2006.01) ,G11C 29/12 (2006.01)
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
5
Details of stores covered by group G11C11/63
14
Power supply arrangements
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
8
Arrangements for selecting an address in a digital store
08
Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
11
Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21
using electric elements
34
using semiconductor devices
40
using transistors
41
forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
413
Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
417
for memory cells of the field-effect type
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
11
Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21
using electric elements
34
using semiconductor devices
40
using transistors
41
forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
413
Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
417
for memory cells of the field-effect type
418
Address circuits
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
29
Checking stores for correct operation; Testing stores during standby or offline operation
04
Detection or location of defective memory elements
08
Functional testing, e.g. testing during refresh, power-on self testing (POST) or distributed testing
12
Built-in arrangements for testing, e.g. built-in self testing (BIST)
Applicants:
QUALCOMM INCORPORATED [US/US]; Attn: International IP Administration 5775 Morehouse Drive San Diego, California 92121-1714, US
Inventors:
JUNG, Chulmin; US
AHMED, Fahad; US
YOON, Sei Seung; US
KIM, Keejong; US
Agent:
GELFOUND, Craig A.; US
HODGES, Jonas J.; US
HARRIMAN, John D.; US
BINDSEIL, James; US
Priority Data:
15/010,38529.01.2016US
Title (EN) MEMORY CELL SCREEN FOR BTI EFFECT
(FR) ÉCRAN DE CELLULE DE MÉMOIRE POUR EFFET BTI
Abstract:
(EN) A memory and a method to operate the memory are provided. The memory includes a plurality of memory cells and a wordline driver configured to output a wordline. The memory cells are coupled to the wordline. A control circuit is configured to supply an operating voltage to the memory cells and to the wordline driver. A voltage-adjustment circuit is configured to adjust the operating voltage supplied to the memory cells during the control circuit supplying the operating voltage to the memory cells and to the wordline driver. The method includes supplying an operating voltage to at least one memory cells and to a wordline coupled to the at least one memory cells and adjusting the operating voltage supplied to the at least one memory cells during the supplying the operating voltage to the at least one memory cells and to the wordline.
(FR) L'invention concerne une mémoire et un procédé de fonctionnement de la mémoire. La mémoire comprend une pluralité de cellules de mémoire et un circuit d'attaque de ligne de mots configuré pour émettre une ligne de mots. Les cellules de mémoire sont couplées à la ligne de mots. Un circuit de commande est configuré pour fournir une tension de fonctionnement aux cellules de mémoire et au circuit d'attaque de ligne de mots. Un circuit de réglage de tension est configuré pour ajuster la tension de fonctionnement fournie aux cellules de mémoire pendant la fourniture, par le circuit de commande, de la tension de fonctionnement aux cellules de mémoire et au circuit d'attaque de ligne de mots. Le procédé consiste à fournir une tension de fonctionnement à au moins une cellule de mémoire et à une ligne de mots couplée à ladite cellule de mémoire, et régler la tension de fonctionnement fournie à ladite cellule de mémoire pendant la fourniture de la tension de fonctionnement à ladite cellule de mémoire et à la ligne de mots.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
CN108604457