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1. (WO2017131643) STABLE THRESHOLD SWITCHING MATERIALS FOR SELECTORS OF RESISTIVE MEMORIES
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What is claimed is:

1 . A stable threshold switching material for selectors employed in resistive memories, the material being amorphous and having a composition given by (V, Nb)i-X- (Si, Hf, W)xOy, where 0 < x < 1 and y is within a range of 1 .5 to 3.

2. The stable threshold switching material of claim 1 wherein the material comprises Nbx-iSixOy alloy, where x is within a range of 0.01 to 0.9 and y is within a range of 2 to 2.5 .

3. The stable threshold switching material of claim 1 wherein the selector is combined in series with a memory element to form a memory cell.

4. The stable threshold switching material of claim 3 wherein the memory element is a resistive memory element.

5. The stable threshold switching material of claim 3 wherein the memory element comprises a material selected from the group consisting of tantalum oxide, titanium oxide, yttrium oxide, hafnium oxide, niobium oxide, zirconium oxide, aluminum oxide, calcium oxide, magnesium oxide, dysprosium oxide, lanthanum oxide, silicon dioxide, or other like oxides aluminum nitride, gallium nitride, tantalum nitride, and silicon nitride and combinations thereof.

6. The stable threshold switching material of claim 3 wherein the memory cell has an electrode contacting the memory element, an other electrode contacting the selector, and an intermediate electrode contacting both the memory element and the selector.

7. The stable threshold switching material of claim 6 wherein each electrode is independently selected from the group consisting of TiN, W, WN2, Ta, TaN, Nb, NbN, Al, Cu, Ti, Pt, Ir, Ru, Ir02, Ru02, Pd, Ni, Ag, Au, Mo, and Co.

8. A method for manufacturing a stable threshold switch comprising a memory element and a selector, one electrode contacting the resistive memory, an other electrode contacting the selector, and an intermediate electrode between the memory element and the selector, the method including forming in either order the memory element and the selector, wherein the selector is formed in an amorphous state and has a composition given by (V, Nb)i-x(Si, Hf, W)xOy, where 0 < x < 1 and y is within a range of 1 .5 to 3.

9. The method of claim 8 wherein the selector is deposited as a film by sputtering a (V, Nb)-(Si, Hf, W) alloy target with an oxygen-containing gas selected from the group consisting of oxygen and water vapor.

10. The method of claim 8 wherein the selector is deposited as a film by sputtering a (V, Nb)Ozi-(Si, Hf, W)Oz2 alloy target with or without oxygen, where z1 is within a range of 2 to 2.5 and z2 is within a range of 2 to 3.

1 1. The method of claim 8 wherein the selector is deposited as a film by Atomic Layer Deposition comprising:

introducing a (V, Nb)-containing volatile precursor to a surface with 0- or OH-terminations;

exposing the surface to an oxygen-containing gas so that oxygen in the oxygen-containing gas can react with the (V, Nb) precursor to form (V, Nb)Oz, where z is within a range of 2 to 2.5;

introducing a (Si, Hf, W)-containing volatile precursor to the surface;

exposing the surface to an oxygen-containing gas so that oxygen in the oxygen-containing gas can react with the (Si, Hf, W) precursor to form (Si, Hf, W)Oz, where z is within a range of 1 .5 to 3; and

repeating the foregoing steps until the film having a desired thickness and composition is obtained.

12. The method of claim 1 1 wherein the Nb-containing volatile precursor is selected from the group consisting of Nb(N(CH3)2)5 and Nb(OCH2CH3) and wherein the Si-containing volatile precursor is selected from the group consisting of

SiH(N(CH3)2), Si(OC2H5)4, Si((CH2)3NH2)(OC2H5), SiCI4, Si(OH)(OC(CH3)3)3, and Si(OH)(OC(CH3)2(C2H5))3.

13. An array of stable threshold switches comprising a plurality of memory cells, each memory cell comprising a memory element and a selector, wherein each selector is amorphous and has a composition given by (V, Nb) -x(Si, Hf, W)xOy, where 0 < x < 1 and y is within a range of 1 .5 to 3.

14. The array of claim 13 in which each memory cell is at a cross point in a 2D crossbar array.

15. The array of claim 13 in which each memory cell is incorporated in a stack of memory cells in a 3D crossbar array.