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1. (WO2017131636) UTILIZING NON-VOLATILE PHASE CHANGE MEMORY IN OFFLINE STATUS AND ERROR DEBUGGING METHODOLOGIES
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What Is Claimed Is:

1 . An apparatus comprising:

a plurality of resistive elements;

a fault detector (204) to determine when a fault corresponding to an integrated circuit (1 00) has occurred; and

a status determiner (206) to, when first data related to the integrated circuit (100) is updated, store the first data in a first subset of the plurality of resistive elements, the status determiner (206) to, in response to the detection of the fault, store second data in a second subset of the plurality of resistive elements, the second data corresponding to an error associated with the fault.

2. The apparatus of claim 1 , wherein the plurality of resistive elements are memristors.

3. The apparatus of claim 1 , wherein the first data includes an identifier identifying at least one of the integrated circuit (100), firmware utilized by the integrated circuit (1 00), software utilized by to the integrated circuit (1 00), hardware corresponding to the integrated circuit (1 00), a temperature corresponding to the integrated circuit (100), or a component associated with the integrated circuit (100).

4. The apparatus of claim 1 , wherein the status determiner (206) is to determine that the integrated circuit (100) has been updated by polling the integrated circuit (1 00).

5. The apparatus of claim 1 , wherein the second data includes a timestamp corresponding to when the fault occurred.

6. The apparatus of claim 1 , wherein the first data and the second data can be read without powering the integrated circuit (100).

7. The apparatus of claim 1 , wherein the status determiner (206) is to, when an error associated with the fault causes the integrated circuit (100) to re-boot, transmit the first data to the integrated circuit (100) prior to the re-booting.

8. A method comprising:

determining when a fault corresponding to an integrated circuit (100) has occurred;

when first data related to the integrated circuit (100) is updated, storing the first data in a first subset of a plurality of resistive elements; and

in response to the detection of the fault, storing second data in a second subset of the plurality of resistive elements, the second data corresponding to an error associated with the fault.

9. The method of claim 8, wherein the plurality of resistive elements are memristors.

10. The method of claim 8, wherein the first data includes an identifier identifying at least one of the integrated circuit (100), firmware utilized by the integrated circuit (1 00), software utilized by to the integrated circuit (1 00), hardware corresponding to the integrated circuit (1 00), a temperature corresponding to the integrated circuit (100), or a component associated with the integrated circuit (100).

1 1 . The method of claim 8, further including polling the integrated circuit (100) to determine when the first data has been updated.

12. The method of claim 8, wherein the second data includes a timestamp corresponding to when the fault occurred.

13. The method of claim 8, wherein the first data and the second data can be read without powering the integrated circuit (100).

14. The method of claim 8, further including, when an error associated with the fault causes the integrated circuit to re-boot, transmitting the first data to the integrated circuit (1 00) prior to the re-booting.

15. A computer readable medium comprising instructions that, when executed, cause a machine to:

determine when a fault corresponding to an integrated circuit (100) has occurred;

when first data related to the integrated circuit (100) is updated, store the first data in a first subset of a plurality of resistive elements; and

in response to the detection of the fault, store second data in a second subset of the plurality of resistive elements, the second data corresponding to an error associated with the fault.