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1. (WO2017130878) SWITCHING AMPLIFIER
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/130878 International Application No.: PCT/JP2017/002053
Publication Date: 03.08.2017 International Filing Date: 23.01.2017
IPC:
H03K 19/0185 (2006.01) ,H03K 17/687 (2006.01) ,H03K 19/003 (2006.01) ,H03K 19/0948 (2006.01)
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
19
Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
0175
Coupling arrangements; Interface arrangements
0185
using field-effect transistors only
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
17
Electronic switching or gating, i.e. not by contact-making and -breaking
51
characterised by the use of specified components
56
by the use, as active elements, of semiconductor devices
687
the devices being field-effect transistors
[IPC code unknown for H03K 19/03]
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
19
Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
02
using specified components
08
using semiconductor devices
094
using field-effect transistors
0944
using MOSFET
0948
using CMOS
Applicants:
日本電気株式会社 NEC CORPORATION [JP/JP]; 東京都港区芝五丁目7番1号 7-1, Shiba 5-chome, Minato-ku, Tokyo 1088001, JP
Inventors:
山瀬 知行 YAMASE Tomoyuki; JP
堀 真一 HORI Shinichi; JP
谷尾 真明 TANIO Masaaki; JP
Agent:
下坂 直樹 SHIMOSAKA Naoki; JP
Priority Data:
2016-01197926.01.2016JP
Title (EN) SWITCHING AMPLIFIER
(FR) AMPLIFICATEUR À COMMUTATION
(JA) スイッチング増幅器
Abstract:
(EN) This switching amplifier is provided with a first CMOS inverter circuit including a first PMOS transistor, and a second PMOS transistor. The source terminal of the first PMOS transistor and the drain terminal of the second PMOS transistor are connected, and the input signal to the gate terminal of the second PMOS transistor changes.
(FR) La présente invention concerne un amplificateur à commutation qui est doté d’un premier circuit inverseur à CMOS comportant un premier transistor PMOS et un second transistor PMOS. La borne de source du premier transistor PMOS et la borne de drain du second transistor PMOS sont connectées et le signal d’entrée vers la borne de grille du second transistor PMOS change.
(JA) 本発明のスイッチング増幅器は、第1のPMOSトランジスタを含む第1のCMOSインバータ回路と、第2のPMOSトランジスタと、を備え、前記第1のPMOSトランジスタのソース端子と前記第2のPMOSトランジスタのドレイン端子とが接続され、前記第2のPMOSトランジスタのゲート端子への入力信号が変化する。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)