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1. (WO2017130776) SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/130776 International Application No.: PCT/JP2017/001252
Publication Date: 03.08.2017 International Filing Date: 16.01.2017
IPC:
H01L 21/336 (2006.01) ,G09F 9/00 (2006.01) ,G09F 9/30 (2006.01) ,H01L 21/3205 (2006.01) ,H01L 21/768 (2006.01) ,H01L 23/522 (2006.01) ,H01L 23/532 (2006.01) ,H01L 29/786 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
G PHYSICS
09
EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
F
DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
9
Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
G PHYSICS
09
EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
F
DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
9
Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
30
in which the desired character or characters are formed by combining individual elements
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3205
Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
768
Applying interconnections to be used for carrying current between separate components within a device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
522
including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
522
including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
532
characterised by the materials
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
Applicants:
シャープ株式会社 SHARP KABUSHIKI KAISHA [JP/JP]; 大阪府堺市堺区匠町1番地 1, Takumi-cho, Sakai-ku, Sakai City, Osaka 5908522, JP
Inventors:
斉藤 貴翁 SAITOH Takao; --
神崎 庸輔 KANZAKI Yohsuke; --
中澤 淳 NAKAZAWA Makoto; --
伊東 一篤 ITO Kazuatsu; --
金子 誠二 KANEKO Seiji; --
Agent:
奥田 誠司 OKUDA Seiji; JP
Priority Data:
2016-01298227.01.2016JP
Title (EN) SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
(FR) DISPOSITIF À SEMI-CONDUCTEURS ET SON PROCÉDÉ DE FABRICATION
(JA) 半導体装置およびその製造方法
Abstract:
(EN) This semiconductor device is provided with a first thin film transistor (101) having a crystalline silicon semiconductor layer (13) and a second thin film transistor (102) having an oxide semiconductor layer (23). First source/drain electrodes (31, 33) of the first thin film transistor (101) are provided on the crystalline silicon semiconductor layer with a first interlayer insulating layer (L1) being interposed therebetween. A second source electrode (25S) of the second thin film transistor (102) is electrically connected to a wiring line (35) that is formed of the same conductive film as the first source/drain electrodes. The wiring line (35) is provided on the second source electrode (25S) with a second interlayer insulating layer (L2) being interposed therebetween, and is in contact with the second source electrode (25S) within a second contact hole that comprises an opening formed in the second interlayer insulating layer (L2). The second source electrode has a multilayer structure including a main layer (25m) and an upper layer (25u) arranged on the main layer; the upper layer (25u) has a first opening below the opening of the second interlayer insulating layer, while the main layer (25m) has a second opening (p2) or a recessed part below the opening of the second interlayer insulating layer; and the second opening (p2) or the recessed part is larger than the first opening (p1) when viewed from the normal direction of a substrate.
(FR) L'invention concerne un dispositif à semi-conducteurs qui comprend un premier transistor à couches minces (101) comprenant une couche de silicium cristallin semi-conducteur (13) et un second transistor à couches minces (102) comprenant une couche d'oxyde semi-conducteur (23). Des premières électrodes de source/drain (31, 33) du premier transistor à couches minces (101) sont disposées sur la couche de silicium cristallin semi-conducteur avec une première couche d'isolation intercouche (L1) intercalée entre elles. Une seconde électrode de source (25S) du second transistor à couches minces (102) est électriquement connectée à une ligne de câblage (35) qui est formée du même film conducteur que les premières électrodes de source/drain. La ligne de câblage (35) est disposée sur la seconde électrode de source (25S) avec une seconde couche d'isolation intercouche (L2) intercalée entre elles, et est en contact avec la seconde électrode de source (25S) à l'intérieur d'un second trou de contact qui comprend une ouverture formée dans la seconde couche d'isolation intercouche (L2). La seconde électrode de source présente une structure multicouche comprenant une couche principale (25m) et une couche supérieure (25u) agencée sur la couche principale ; la couche supérieure (25u) présente une première ouverture au-dessous de l'ouverture de la seconde couche d'isolation intercouche, tandis que la couche principale (25m) présente une seconde ouverture (p2) ou une partie évidée au-dessous de l'ouverture de la seconde couche d'isolation intercouche ; et, vues dans la direction normale d'un substrat, la seconde ouverture (p2) ou la partie évidée est plus grande que la première ouverture (p1).
(JA) 半導体装置は、結晶質シリコン半導体層(13)を有する第1薄膜トランジスタ(101)と、酸化物半導体層(23)を有する第2薄膜トランジスタ(102)とを備え、第1薄膜トランジスタ(101)の第1ソース・ドレイン電極(31)、(33)は、結晶質シリコン半導体層の上に第1の層間絶縁層(L1)を介して設けられ、第2薄膜トランジスタ(102)の第2ソース電極(25S)は、第1ソース・ドレイン電極と同じ導電膜から形成された配線(35)に電気的に接続されており、配線(35)は、第2ソース電極(25S)の上に第2の層間絶縁層(L2)を介して設けられ、かつ、第2の層間絶縁層(L2)に形成された開口を含む第2コンタクトホール内で第2ソース電極(25S)と接し、第2ソース電極は、主層(25m)と、主層の上に配置された上層(25u)とを含む積層構造を有し、第2の層間絶縁層の開口の下方において、上層(25u)は第1開口部を有し、主層(25m)は第2開口部(p2)または凹部を有し、基板の法線方向から見たとき、第2開口部(p2)または凹部は第1開口部(p1)よりも大きい。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)
Also published as:
CN108496244US20190035824