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1. (WO2017130728) SOLID-STATE IMAGING DEVICE AND ELECTRONIC DEVICE
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/130728 International Application No.: PCT/JP2017/000930
Publication Date: 03.08.2017 International Filing Date: 13.01.2017
IPC:
H01L 27/146 (2006.01) ,H01L 21/76 (2006.01) ,H04N 5/369 (2011.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
14
including semiconductor components sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
144
Devices controlled by radiation
146
Imager structures
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
76
Making of isolation regions between components
H ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
N
PICTORIAL COMMUNICATION, e.g. TELEVISION
5
Details of television systems
30
Transforming light or analogous information into electric information
335
using solid-state image sensors [SSIS]
369
SSIS architecture; Circuitry associated therewith
Applicants:
ソニー株式会社 SONY CORPORATION [JP/JP]; 東京都港区港南1丁目7番1号 1-7-1, Konan, Minato-ku, Tokyo 1080075, JP
Inventors:
滝沢 正明 TAKIZAWA Masaaki; JP
舘下 八州志 TATESHITA Yasushi; JP
豊島 隆寛 TOYOSHIMA Takahiro; JP
豊福 卓哉 TOYOFUKU Takuya; JP
坂野 頼人 SAKANO Yorito; JP
鳥居 元展 TORII Motonobu; JP
Agent:
西川 孝 NISHIKAWA Takashi; JP
稲本 義雄 INAMOTO Yoshio; JP
Priority Data:
2016-01654829.01.2016JP
Title (EN) SOLID-STATE IMAGING DEVICE AND ELECTRONIC DEVICE
(FR) DISPOSITIF D'IMAGERIE À SEMICONDUCTEUR ET DISPOSITIF ÉLECTRONIQUE
(JA) 固体撮像装置および電子機器
Abstract:
(EN) The present disclosure relates to a solid-state imaging device and an electronic device designed so as to capable of reducing optical crosstalk. In example B in fig. 5, a charge storage part is configured by boring a hole in a substrate, forming a diffusion layer on the surface of the hole, and forming an insulating film and an upper electrode so as to fill the hole. In example C in fig. 5, the charge storage part is configured by boring a hole in a substrate, forming a diffusion layer on half (one side) of the surface of the hole, and forming an insulation film and an upper electrode so as to fill the hole. The charge storage part (capacitive element) formed in the substrate as described above is positioned between photodiodes, which constitute a first photoelectric converter, whereby the capacitive element can play the role of a shield pair against crosstalk between the photodiodes in a unit pixel. The present disclosure is applicable, for example, to a CMOS solid-state imaging device used in an imaging device such as a camera.
(FR) La présente invention concerne un dispositif d'imagerie à semiconducteur et un dispositif électronique conçu pour être capable de réduire la diaphonie optique. Dans l'exemple B dans la Figure 5, une partie de stockage de charge est configurée en perçant un trou dans un substrat, en formant une couche de diffusion sur la surface du trou et en formant un film isolant et une électrode supérieure de manière à remplir le trou. Dans l'exemple C dans la Figure 5, la partie de stockage de charge est configurée en perçant un trou dans un substrat, en formant une couche de diffusion sur la moitié (un côté) de la surface du trou et en formant un film isolant et une électrode supérieure de manière à remplir le trou. La partie de stockage de charge (élément capacitif) formée dans le substrat comme décrit ci-dessus est positionnée entre des photodiodes qui constituent un premier convertisseur photoélectrique. L'élément capacitif peut ainsi jouer le rôle d'une paire de blindage contre la diaphonie entre les photodiodes dans un pixel unitaire. La présente invention peut être appliquée, par exemple, à un dispositif d'imagerie à semiconducteur CMOS utilisé dans un dispositif d'imagerie tel qu'un appareil photographique.
(JA) 本開示は、光学的クロストークを低減することができるようにする固体撮像装置および電子機器に関する。 図5のBの例の場合、電荷蓄積部は、基板に孔を掘り、孔の表面に拡散層が形成され、孔を埋めるように、絶縁膜および上部電極が形成されることによって、構成される。図5のCの例の場合、電荷蓄積部は、基板に孔を掘り、孔の表面の半分(片側)に拡散層が形成され、孔を埋めるように、絶縁膜および上部電極が形成されることによって、構成される。以上のようにして基板中に形成される電荷蓄積部(容量素子)を第1光電変換部であるPDの間に配置することにより、単位画素において、容量素子がPD間のクロストークに対する遮蔽対の役割を果たすことができる。本開示は、例えば、カメラなどの撮像装置に用いられるCMOS固体撮像装置に適用することができる。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)
Also published as:
CN108475691US20190019820