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1. (WO2017130723) SOLID-STATE IMAGE CAPTURE ELEMENT AND ELECTRONIC DEVICE
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/130723 International Application No.: PCT/JP2017/000923
Publication Date: 03.08.2017 International Filing Date: 13.01.2017
IPC:
H01L 27/146 (2006.01) ,G02B 7/34 (2006.01) ,H01L 21/76 (2006.01) ,H04N 5/369 (2011.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
14
including semiconductor components sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
144
Devices controlled by radiation
146
Imager structures
G PHYSICS
02
OPTICS
B
OPTICAL ELEMENTS, SYSTEMS, OR APPARATUS
7
Mountings, adjusting means, or light-tight connections, for optical elements
28
Systems for automatic generation of focusing signals
34
using different areas in a pupil plane
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
76
Making of isolation regions between components
H ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
N
PICTORIAL COMMUNICATION, e.g. TELEVISION
5
Details of television systems
30
Transforming light or analogous information into electric information
335
using solid-state image sensors [SSIS]
369
SSIS architecture; Circuitry associated therewith
Applicants:
ソニー株式会社 SONY CORPORATION [JP/JP]; 東京都港区港南1丁目7番1号 1-7-1, Konan, Minato-ku, Tokyo 1080075, JP
Inventors:
正垣 敦 MASAGAKI Atsushi; JP
田中 裕介 TANAKA Yusuke; JP
Agent:
西川 孝 NISHIKAWA Takashi; JP
稲本 義雄 INAMOTO Yoshio; JP
Priority Data:
2016-01361327.01.2016JP
Title (EN) SOLID-STATE IMAGE CAPTURE ELEMENT AND ELECTRONIC DEVICE
(FR) ÉLÉMENT DE CAPTURE D'IMAGE À SEMICONDUCTEUR ET DISPOSITIF ÉLECTRONIQUE
(JA) 固体撮像素子および電子機器
Abstract:
(EN) The present disclosure relates to a solid-state image capture element and an electronic device in which leakage of charge into adjacent pixels can be prevented. A plurality of pixels performs photoelectric conversion with respect to light incident on a back surface via different on-chip lenses for the respective pixels. A pixel separation wall is formed between adjacent pixels, and comprises a front surface trench which is a trench formed on a front surface, and a back surface trench which is a trench formed on a back surface. The wiring layer is provided on the front surface. The present disclosure may be applied in a back-illuminated CMOS image sensor, for example.
(FR) La présente invention concerne un élément de capture d'image à semiconducteur et un dispositif électronique dans lequel une fuite de charges dans des pixels adjacents peut être évitée. Une pluralité de pixels effectuent une conversion photoélectrique de la lumière incidente sur une surface arrière au moyen de différentes lentilles intégrées à la puce pour les pixels respectifs. Une paroi de séparation des pixels est formée entre des pixels adjacents, et comprend une tranchée de surface avant, c'est-à-dire une tranchée formée sur une surface avant, et une tranchée de surface arrière, c'est-à-dire une tranchée formée sur la surface arrière. La couche de câblage est disposée sur la surface avant. La présente technique peut par exemple être appliquée à un capteur d'image CMOS.
(JA) 本開示は、隣接する画素の間の電荷の漏れ込みを防止することができるようにする固体撮像素子および電子機器に関する。 複数の画素は、画素ごとに異なるオンチップレンズを介して裏面から入射された光に対して光電変換を行う。画素分離壁は、隣接する画素の間に形成され、表面に形成されたトレンチである表面トレンチと、裏面に形成されたトレンチである裏面トレンチとにより構成される。配線層は、表面に設けられる。本開示は、例えば、裏面照射型CMOSイメージセンサ等に適用することができる。
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)
Also published as:
CN107408568KR1020180108414JPWO2017130723US20180350856EP3410487DE112017000216