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1. (WO2017130722) DETECTION DIODE
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/130722 International Application No.: PCT/JP2017/000896
Publication Date: 03.08.2017 International Filing Date: 12.01.2017
IPC:
H01L 29/861 (2006.01) ,H01L 29/205 (2006.01) ,H01L 29/868 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
86
controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated, or switched
861
Diodes
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
12
characterised by the materials of which they are formed
20
including, apart from doping materials or other impurities, only AIIIBV compounds
201
including two or more compounds
205
in different semiconductor regions
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
86
controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated, or switched
861
Diodes
868
PIN diodes
Applicants:
NTTエレクトロニクス株式会社 NTT ELECTRONICS CORPORATION [JP/JP]; 神奈川県横浜市神奈川区新浦島町一丁目1番地32 1-32, Shin-urashimacho 1-chome, Kanagawa-ku, Yokohama-shi, Kanagawa 2210031, JP
学校法人北里研究所 SCHOOL JURIDICAL PERSON KITASATO INSTITUTE [JP/JP]; 東京都港区白金5丁目9番1号 9-1, Shirokane 5-chome, Minato-ku, Tokyo 1088641, JP
Inventors:
伊藤 弘樹 ITOH Hiroki; JP
清水 誠 SHIMIZU Makoto; JP
石橋 忠夫 ISHIBASHI Tadao; JP
伊藤 弘 ITO Hiroshi; JP
Agent:
特許業務法人 谷・阿部特許事務所 TANI & ABE, P.C.; 東京都港区赤坂2丁目6-20 6-20, Akasaka 2-chome, Minato-ku, Tokyo 1070052, JP
Priority Data:
2016-01476928.01.2016JP
Title (EN) DETECTION DIODE
(FR) DIODE DE DÉTECTION
(JA) 検波ダイオード
Abstract:
(EN) To ensure good detection characteristics by suppressing degradation of I-V characteristics of a heterojunction barrier diode (HBD) which operates with zero bias in the THz frequency band. The detection diode is provided with a semiconductor laminated structure, wherein a high concentration n-type first semiconductor layer, a second semiconductor layer having a smaller electron affinity in comparison to that of the first semiconductor layer, and an n-type third semiconductor layer 1 are laminated in order; a heterobarrier is formed at the second semiconductor layer side of an interface between the first semiconductor layer and the second semiconductor layer; the barrier height of the heterobarrier is adjusted by adjusting the doping level of the first semiconductor layer; an anode electrode is formed on the first semiconductor layer; a cathode electrode is formed on the third semiconductor layer; the second semiconductor layer including an undoped barrier layer which contacts the first semiconductor layer, and an n-type barrier layer which contacts the third semiconductor layer.
(FR) La présente invention vise à assurer de bonnes caractéristiques de détection en supprimant la dégradation des caractéristiques I-V d'une diode d'arrêt à hétérojonction (HBD) qui fonctionne avec une polarisation nulle dans la bande de fréquence THz. La diode de détection est dotée d'une structure stratifiée à semi-conducteurs, une première couche semi-conductrice de type n à concentration élevée, une deuxième couche semi-conductrice ayant une affinité électronique plus petite par rapport à celle de la première couche semi-conductrice, et une troisième couche semi-conductrice de type n 1 étant stratifiées dans cet ordre; une hétéro-barrière est formée au niveau du côté deuxième couche semi-conductrice d'une interface entre la première couche semi-conductrice et la deuxième couche semi-conductrice; la hauteur de barrière de l'hétéro-barrière est réglée en réglant le niveau de dopage de la première couche semi-conductrice; une électrode d'anode est formée sur la première couche semi-conductrice; une électrode de cathode est formée sur la troisième couche semi-conductrice; la deuxième couche semi-conductrice comprenant une couche de barrière non dopée qui est en contact avec la première couche semi-conductrice, et une couche de barrière de type n qui est en contact avec la troisième couche semi-conductrice.
(JA) THz周波数帯においてゼロバイアス動作させるHBDにおいて、I-V特性の劣化を抑制することにより、良好な検波特性を確保する。高濃度のn形の第1の半導体層と、前記第1の半導体層と比較してより小さな電子親和力を有する第2の半導体層と、n形の第3の半導体層1とが順に積層され、前記第1の半導体層と前記第2の半導体層との界面の前記第2の半導体層側にヘテロバリアが形成され、前記第1の半導体層のドーピングレベルを調整することにより、前記へテロバリアのバリア高さが調整されており、前記第1の半導体層上にアノード電極が形成され、前記第3の半導体層上にカソード電極が形成された半導体積層構造を備え、前記第2の半導体層は、前記第1の半導体層と接するアンドープのバリア層と、前記第3の半導体層と接するn形のバリア層とを含む。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)