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1. (WO2017130373) METHOD FOR FORMING CIRCUIT ON SUBSTRATE
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/130373 International Application No.: PCT/JP2016/052625
Publication Date: 03.08.2017 International Filing Date: 29.01.2016
IPC:
C23C 18/18 (2006.01) ,H01L 21/288 (2006.01)
C CHEMISTRY; METALLURGY
23
COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
C
COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
18
Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
16
by reduction or substitution, i.e. electroless plating
18
Pretreatment of the material to be coated
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
28
Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/268158
283
Deposition of conductive or insulating materials for electrodes
288
from a liquid, e.g. electrolytic deposition
Applicants:
株式会社JCU JCU CORPORATION [JP/JP]; 東京都台東区東上野4丁目8番1号 TIXTOWER UENO 16階 TIXTOWER UENO 16th floor, 8-1, Higashiueno 4-chome, Taito-ku, Tokyo 1100015, JP
Inventors:
佐土原 大祐 SADOHARA Daisuke; JP
西川 賢一 NISHIKAWA Kenichi; JP
鈴木 啓太 SUZUKI Keita; JP
伊部 公太 IBE Kouta; JP
下田 勝己 SHIMODA Katsumi; JP
Agent:
特許業務法人 小野国際特許事務所 THE PATENT CORPORATE BODY OF ONO & CO.; 東京都中央区日本橋箱崎町20-5 20-5, Nihonbashihakozaki-cho, Chuo-ku, Tokyo 1030015, JP
Priority Data:
Title (EN) METHOD FOR FORMING CIRCUIT ON SUBSTRATE
(FR) PROCÉDÉ DE FORMATION D'UN CIRCUIT SUR UN SUBSTRAT
(JA) 基板上への回路形成方法
Abstract:
(EN) A new method is provided by which a desired portion of a substrate surface can be plated with a metal through a small number of steps regardless of the kind of the substrate, thereby forming a circuit. The method for forming a circuit on a substrate through plating is characterized by including the steps of forming a coating film comprising a silicone oligomer and a catalyst metal on a substrate, thereafter activating the catalyst metal contained in the coating film to make the coating film exhibit autocatalytic properties, and then conducting electroless plating.
(FR) L'invention concerne un nouveau procédé permettant de plaquer avec un métal, en un petit nombre d'étapes, une partie souhaitée d'une surface de substrat indépendamment du type de substrat, pour former ainsi un circuit. Le procédé de formation de circuit sur un substrat par placage est caractérisé en ce qu'il comprend les étapes consistant à former un film de revêtement comprenant un oligomère de silicone et un métal de catalyse sur un substrat, puis à activer le métal de catalyse contenu dans le film de revêtement pour conférer au film de revêtement des propriétés autocatalytiques, et enfin procéder à un placage autocatalytique.
(JA) 基板の種類によらず少ない工程で基板上への所望の部位へ金属めっきを行い回路形成できる新しい方法を提供する。基板上にめっきで回路形成を行うにあたり、 基板上に、シリコンオリゴマーおよび触媒金属を含有するコーティング皮膜を施した後、コーティング皮膜中の触媒金属の活性化処理を行い自己触媒性を発現させ、次いで、無電解めっきを行う工程を含むことを特徴とする基板上への回路形成方法。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)
Also published as:
CN108463576KR1020180103932EP3409814US20190029126