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1. (WO2017128557) ARRAY SUBSTRATE AND LIQUID CRYSTAL DISPLAY DEVICE
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/128557 International Application No.: PCT/CN2016/082104
Publication Date: 03.08.2017 International Filing Date: 13.05.2016
IPC:
G02F 1/1362 (2006.01) ,G02F 1/1368 (2006.01)
G PHYSICS
02
OPTICS
F
DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
1
Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
01
for the control of the intensity, phase, polarisation or colour
13
based on liquid crystals, e.g. single liquid crystal display cells
133
Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
136
Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
1362
Active matrix addressed cells
G PHYSICS
02
OPTICS
F
DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
1
Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
01
for the control of the intensity, phase, polarisation or colour
13
based on liquid crystals, e.g. single liquid crystal display cells
133
Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
136
Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
1362
Active matrix addressed cells
1368
in which the switching element is a three-electrode device
Applicants:
武汉华星光电技术有限公司 WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD [CN/CN]; 中国湖北省武汉市 武汉东湖开发区高新大道666号生物城C5栋 Building C5 No. 666 Gaoxin Avenue, East Lake High-Tech Development Zone Wuhan, Hubei 430070, CN
Inventors:
范广宝 FAN, Guangbao; CN
Agent:
广州三环专利商标代理有限公司 SCIHEAD IP LAW FIRM; 中国广东省广州市 越秀区先烈中路80号汇华商贸大厦1508室 Room 1508, Huihua Commercial &Trade Building No. 80, XianLie Zhong Road, Yuexiu District Guangzhou, Guangdong 510070, CN
Priority Data:
201610047658.725.01.2016CN
Title (EN) ARRAY SUBSTRATE AND LIQUID CRYSTAL DISPLAY DEVICE
(FR) SUBSTRAT MATRICIEL ET DISPOSITIF D'AFFICHAGE À CRISTAUX LIQUIDES
(ZH) 阵列基板及液晶显示装置
Abstract:
(EN) An array substrate (10) and a liquid crystal display device (1). The array substrate (10) comprises multiple low-temperature polycrystalline silicon thin film transistors (100) distributed in an array manner. Each low-temperature polycrystalline silicon thin film transistor (100) comprises a substrate (110), and comprises a low-temperature polycrystalline silicon layer (140), a first insulation layer (150), a gate (160), a second insulation layer (170), a source (180), a drain (190), a flat layer (210), a first transparent conductive layer (220), a third insulation layer (230), a second transparent conductive layer (240) and a connecting metal layer (250) that are disposed on the same side of the substrate (110). The low-temperature polycrystalline silicon layer (140), the gate (160) and the second insulation layer (170) are sequentially stacked, the source (180) and the drain (190) are disposed on the second insulation layer (170) and are connected to the two opposite ends of the low-temperature polycrystalline silicon layer (140) through a first through hole (170a) and a second through hole (170b) that are formed in the second insulation layer (170) respectively. The flat layer (210), the first transparent conductive layer (220), the third insulation layer (230) and the second transparent conductive layer (240) are sequentially stacked. The connecting metal layer (250) is connected to the second transparent conductive layer (240) and the drain (190) through a fourth through hole (231) formed in the third insulation layer (230), the first transparent conductive layer (220) serves as a common electrode, and the second transparent conductive layer (240) serves as a pixel electrode. The pixel electrode and the drain (190) of the low-temperature polycrystalline silicon thin film transistor (100) of the array substrate (10) are electrically connected by means of the connecting metal layer (250), so that the drain (190) can normally charge the pixel electrode, thereby improving the defect-free rate of the liquid crystal display device (1).
(FR) L'invention concerne un substrat matriciel (10) et un dispositif d'affichage à cristaux liquides (1). Le substrat matriciel (10) comprend de multiples transistors en couche mince en silicium polycristallin à basse température (100) répartis d'une manière matricielle. Chaque transistor en couche mince en silicium polycristallin à basse température (100) comprend un substrat (110), et comprend une couche de silicium polycristallin à basse température (140), une première couche isolante (150), une grille (160), une deuxième couche isolante (170), une source (180), un drain (190), une couche plate (210), une première couche conductrice transparente (220), une troisième couche isolante (230), une seconde couche conductrice transparente (240) et une couche métallique de connexion (250) qui sont disposés sur le même côté du substrat (110). La couche de silicium polycristallin à basse température (140), la grille (160) et la seconde couche isolante (170) sont empilées séquentiellement, la source (180) et le drain (190) sont disposés sur la seconde couche isolante (170) et sont connectés aux deux extrémités opposées de la couche de silicium polycristallin à basse température (140) à travers un premier trou traversant (170a) et un deuxième trou traversant (170b) qui sont formés dans la deuxième couche isolante (170) respectivement. La couche plate (210), la première couche conductrice transparente (220), la troisième couche isolante (230) et la seconde couche conductrice transparente (240) sont séquentiellement empilées. La couche métallique de connexion (250) est connectée à la seconde couche conductrice transparente (240) et au drain (190) par l'intermédiaire d'un quatrième trou traversant (231) formé dans la troisième couche isolante (230), la première couche conductrice transparente (220) sert d'électrode commune, et la seconde couche conductrice transparente (240) sert d'électrode de pixel. L'électrode de pixel et le drain (190) du transistor en couche mince en silicium polycristallin à basse température (100) du substrat matriciel (10) sont électriquement connectés au moyen de la couche métallique de connexion (250), de telle sorte que le drain (190) peut normalement charger l'électrode de pixel, ce qui permet d'améliorer le taux sans défaut du dispositif d'affichage à cristaux liquides (1).
(ZH) 一种阵列基板(10)及液晶显示装置(1),所述阵列基板(10)包括呈阵列分布的多个低温多晶硅薄膜晶体管(100),所述低温多晶硅薄膜晶体管(100)包括:基板(110)及设置在基板(110)同侧的低温多晶硅层(140)、第一绝缘层(150)、栅极(160)、第二绝缘层(170)、源极(180)、漏极(190)、平坦层(210)、第一透明导电层(220)、第三绝缘层(230)、第二透明导电层(240)及连接金属层(250),所述低温多晶硅层(140)、栅极(160)、第二绝缘层(170)依次层叠设置,源极(180)及漏极(190)设置在第二绝缘层(170)上,并分别通过第二绝缘层(170)上的第一贯孔(170a)与第二贯孔(170b)连接低温多晶硅层(140)相对的两端,所述平坦层(210)、第一透明导电层(220)、第三绝缘层(230)及第二透明导电层(240)依次层叠设置,所述连接金属层(250)通过第三绝缘层(230)的第四贯孔(231)连接第二透明导电层(240)及漏极(190),其中,第一透明导电层(220)为公共电极,第二透明导电层(240)为像素电极。所述阵列基板(10)的低温多晶硅薄膜晶体管(100)像素电极及漏极(190)通过所述连接金属层(250)电连接,从而使得漏极(190)能够对像素电极正常充电,提高了所述液晶显示装置(1)的良率。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)
Also published as:
US20180059455