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1. (WO2017112349) CRACK RESISTANT ELECTRONIC DEVICE PACKAGE SUBSTRATES
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/112349 International Application No.: PCT/US2016/063798
Publication Date: 29.06.2017 International Filing Date: 26.11.2016
IPC:
H01L 23/498 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
488
consisting of soldered or bonded constructions
498
Leads on insulating substrates
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors:
CAI, Yuhong; US
GOGINENI, Sireesha; US
YAP, John; US
Agent:
OSBORNE, David W.; US
Priority Data:
14/998,22926.12.2015US
Title (EN) CRACK RESISTANT ELECTRONIC DEVICE PACKAGE SUBSTRATES
(FR) SUBSTRATS RÉSISTANT AUX FISSURES POUR BOÎTIERS DE DISPOSITIFS ÉLECTRONIQUES
Abstract:
(EN) Crack resistant electronic device package substrate technology is disclosed. In an example, an electronic device package substrate can include a substrate core material having a surface. The substrate can also include a solder ball pad coupled to the surface of the substrate. In addition, the substrate can include a layer of solder resist material coupled to the surface of the substrate at a location that leaves a gap in between a lateral side of the solder ball pad and the solder resist material.
(FR) L'invention concerne la technologie des substrats résistant aux fissures pour boîtiers de dispositifs électroniques. Dans un exemple, un substrat pour boîtier de dispositif électronique peut comprendre un matériau de cœur de substrat présentant une surface. Le substrat peut également comprendre une plage à bille de soudure couplée à la surface du substrat. De plus, le substrat peut comprendre une couche de matériau de réserve de substrat couplée à la surface du substrat à un endroit qui ménage un écartement entre un côté latéral de la plage à bille de soudure et le matériau de réserve de substrat.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)