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1. (WO2017112209) LINEAR LOW NOISE AMPLIFIER
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/112209 International Application No.: PCT/US2016/063060
Publication Date: 29.06.2017 International Filing Date: 21.11.2016
Chapter 2 Demand Filed: 20.10.2017
IPC:
H03F 3/195 (2006.01) ,H03F 1/32 (2006.01)
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
F
AMPLIFIERS
3
Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
189
High-frequency amplifiers, e.g. radio frequency amplifiers
19
with semiconductor devices only
195
in integrated circuits
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
F
AMPLIFIERS
1
Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
32
Modifications of amplifiers to reduce non-linear distortion
Applicants:
QUALCOMM INCORPORATED [US/US]; ATTN: International IP Administration 5775 Morehouse Drive San Diego, California 92121-1714, US
Inventors:
MASNADI SHIRAZI NEJAD, Amir Hossein; US
TAGHIVAND, Mazhareddin; US
MIRI LAVASANI, Sayed Hossein; US
EMADI, Mohammad; US
Agent:
PARADICE, William L., III; US
Priority Data:
15/174,85606.06.2016US
62/271,14322.12.2015US
Title (EN) LINEAR LOW NOISE AMPLIFIER
(FR) AMPLIFICATEUR À FAIBLE BRUIT LINÉAIRE
Abstract:
(EN) A linear low noise amplifier is disclosed. In at least one exemplary embodiment, the linear low noise amplifier may include a first metal oxide semiconductor field effect transistor (MOSFET) configured to operate in a triode mode coupled to a second MOSFET configured to operate in a saturation mode. Linearity of the low noise amplifier may be determined, at least in part, by a transconductance associated with the second MOSFET and a channel resistance associated the first MOSFET.
(FR) L'invention concerne un amplificateur à faible bruit (LNA) linéaire. Dans au moins un exemple de mode de réalisation, l'amplificateur à faible bruit linéaire peut comprendre un premier transistor à effet de champ métal-oxyde-semi-conducteur (MOSFET) configuré pour fonctionner dans un mode triode, couplé à un second MOSFET configuré pour fonctionner dans un mode de saturation. La linéarité de l'amplificateur à faible bruit peut être déterminée, au moins en partie, par une transconductance associée au second MOSFET et une résistance de canal associée au premier MOSFET.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)