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1. (WO2017112196) DUAL-LAYER DIELECTRIC IN MEMORY DEVICE
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/112196 International Application No.: PCT/US2016/062954
Publication Date: 29.06.2017 International Filing Date: 18.11.2016
IPC:
H01L 27/115 (2017.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
105
including field-effect components
112
Read-only memory structures
115
Electrically programmable read-only memories
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors:
BERNHARDT, Michael J.; US
KIM, Yudong; US
FROST, Denzil S.; US
ALLEN, III, Tuman Earl; US
BAKER, Kevin Lee; US
YASTREBENETSKY, Kolya; US
WEIMER, Ronald Allen; US
Agent:
PARKER, Wesley E.; US
WANG, Yuke; US
RASKIN, Vladimir; US
AUYEUNG, Al; US
STRAUSS, Ryan N.; US
MOORE, Michael S.; US
MAKI, Nathan R.; US
BLAIR, Steven R.; US
DANSKIN, Timothy A.; US
MARLINK, Jeffrey S.; US
MEININGER, Mark M.; US
LEE, Katherine D.; US
COWGER, Graciela G.; US
KIRKPATRICK, Bryan D.; US
COFIELD, Michael A.; US
Priority Data:
14/998,19423.12.2015US
Title (EN) DUAL-LAYER DIELECTRIC IN MEMORY DEVICE
(FR) DIÉLECTRIQUE DOUBLE COUCHE DANS UN DISPOSITIF DE MÉMOIRE
Abstract:
(EN) Embodiments of the present disclosure describe techniques and configurations for a memory device comprising a memory array having a plurality of wordlines disposed in a memory region of a die. Fill regions may be disposed between respective pairs of adjacent wordlines of the plurality of wordlines. The fill regions may include a first dielectric layer and a second dielectric layer disposed on the first dielectric layer. The first dielectric layer may comprise organic (e.g., carbon-based) spin-on dielectric material (CSOD). The second dielectric layer may comprise a different dielectric material than the first dielectric layer, such as, for example, inorganic dielectric material. Other embodiments may be described and/or claimed.
(FR) La présente invention concerne, selon des modes de réalisation, des techniques et des configurations d'un dispositif de mémoire comprenant une matrice mémoire ayant une pluralité de lignes de mots positionnée dans une région de mémoire d'une puce. Des zones de remplissage peuvent être positionnées entre des paires respectives de lignes de mots adjacentes parmi la pluralité de lignes de mots. Les zones de remplissage peuvent comprendre une première couche diélectrique et une seconde couche diélectrique placée sur la première couche diélectrique. La première couche diélectrique peut comprendre un matériau diélectrique organique (par exemple à base de carbone) déposé par rotation (CSOD). La seconde couche diélectrique peut comprendre un matériau diélectrique différent de celui de la première couche diélectrique, tel que, par exemple, un matériau diélectrique inorganique. D'autres modes de réalisation peuvent être décrits et/ou revendiqués.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
CN108307662DE112016006040BR112018012787