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1. (WO2017112162) INCREASING THREAD PAYLOAD FOR 3D PIPELINE WITH WIDER SIMD EXECUTION WIDTH
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/112162 International Application No.: PCT/US2016/062463
Publication Date: 29.06.2017 International Filing Date: 17.11.2016
IPC:
G06F 9/48 (2006.01) ,G06F 9/38 (2006.01) ,G06T 15/80 (2011.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
9
Arrangements for programme control, e.g. control unit
06
using stored programme, i.e. using internal store of processing equipment to receive and retain programme
46
Multiprogramming arrangements
48
Programme initiating; Programme switching, e.g. by interrupt
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
9
Arrangements for programme control, e.g. control unit
06
using stored programme, i.e. using internal store of processing equipment to receive and retain programme
30
Arrangements for executing machine- instructions, e.g. instruction decode
38
Concurrent instruction execution, e.g. pipeline, look ahead
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
T
IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
15
3D [Three Dimensional] image rendering
50
Lighting effects
80
Shading
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors:
VENKATESH, Jayashree; US
CHEN, Gang; US
RAOUX, Thomas F.; US
LUEH, Guei-Yuan; US
MAIYURAN, Maiyuran; US
Agent:
KOMENDA, J. Kyle; US
Priority Data:
14/976,12221.12.2015US
Title (EN) INCREASING THREAD PAYLOAD FOR 3D PIPELINE WITH WIDER SIMD EXECUTION WIDTH
(FR) AUGMENTATION DE DONNÉES UTILES DE FIL POUR UN PIPELINE 3D AVEC UNE LARGEUR D'EXÉCUTION DE SIMD PLUS LARGE
Abstract:
(EN) Reducing SIMD fragmentation for SIMD execution widths of 32 or even 64 channels in a single hardware thread leads to better EU utilization. Increasing SIMD execution widths to 32 or 64 channels per thread, enables handling more vertices, patches, primitives and triangles per EU hardware thread. Modified 3D pipeline shader payloads can handle multiple patches in case of domain shaders or multiple primitives when primitive object instance count is greater than one in the case of geometry shaders and multiple triangles in case of pixel shaders.
(FR) Selon l'invention, une réduction de fragmentation de SIMD pour des largeurs d'exécution de SIMD de 32 ou même 64 canaux dans un fil matériel unique conduit à une meilleure utilisation d'EU. Augmenter des largeurs d'exécution de SIMD à 32 ou 64 canaux par fil permet un traitement de davantage de sommets, de pièces, de primitives et de triangles par fil matériel d'EU. Des données utiles de nuanceur de pipeline 3D modifiées peuvent traiter de multiples pièces dans le cas de nuanceurs de domaine ou de multiples primitives lorsqu'un décompte d'instances d'objet de primitive est supérieur à un dans le cas de nuanceurs de géométrie et de multiples triangles dans le cas de nuanceurs de pixel.
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
EP3394748