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1. (WO2017112136) INTEGRATED CIRCUIT PACKAGE SUPPORT STRUCTURES
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/112136 International Application No.: PCT/US2016/062146
Publication Date: 29.06.2017 International Filing Date: 16.11.2016
IPC:
H01L 23/34 (2006.01) ,H01L 23/00 (2006.01) ,H01L 23/48 (2006.01) ,H01L 23/498 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
34
Arrangements for cooling, heating, ventilating or temperature compensation
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
488
consisting of soldered or bonded constructions
498
Leads on insulating substrates
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054-1549, US
Inventors:
HUI, Michael; US
YEE, Rashelle; US
THIBADO, Jonathan; US
CARTER, Daniel P.; US
FERGUSON, Shelby; US
VALPIANI, Anthony P.; US
AOKI, Russell S.; US
CARSTENS, Jonathon Robert; US
JASNIEWSKI, Joseph J.; US
KOFSTAD, Harvey R.; US
BRAZEL, Michael; US
CLACK, Tracy; US
VOGMAN, Viktor; US
WOODCOCK, Penny; US
CEURTER, Kevin J.; US
YAN, Hongfei; US
Agent:
ZAGER, Laura A.; US
Priority Data:
14/975,94321.12.2015US
Title (EN) INTEGRATED CIRCUIT PACKAGE SUPPORT STRUCTURES
(FR) STRUCTURES DE SUPPORT DE BOÎTIERS DE CIRCUITS INTÉGRÉS
Abstract:
(EN) Disclosed herein are integrated circuit (IC) package support structures, and related systems, devices, and methods. In some embodiments, an IC package support structure may include a first heater trace, and a second heater trace, wherein the second heater trace is not conductively coupled the first heater trace in the IC package support structure.
(FR) L'invention concerne des structures de support de boîtiers de circuits intégrés (CI), et des systèmes, des dispositifs et des procédés associés. Dans certains modes de réalisation, une structure de support de boîtier de circuit intégré, peut comprendre une première trace chauffante, et une seconde trace chauffante, la seconde trace chauffante n'étant pas couplée de manière conductrice à la premier trace chauffante dans la structure de support de boîtier de circuit intégré.
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
DE112016005862