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1. (WO2017112043) STRUCTURES TO MITIGATE CONTAMINATION ON A BACK SIDE OF A SEMICONDUCTOR SUBSTRATE
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/112043 International Application No.: PCT/US2016/056860
Publication Date: 29.06.2017 International Filing Date: 13.10.2016
IPC:
H01L 23/00 (2006.01) ,H01L 21/78 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors:
BRUN, Xavier F.; US
AGRAWAL, Shweta; US
WU, Hao; US
MAMODIA, Mohit; US
OU, Shengquan E.; US
SHI, Hualiang; US
Agent:
BRASK, Justin, K.; US
Priority Data:
14/998,09623.12.2015US
Title (EN) STRUCTURES TO MITIGATE CONTAMINATION ON A BACK SIDE OF A SEMICONDUCTOR SUBSTRATE
(FR) STRUCTURES PERMETTANT D'ATTÉNUER LA CONTAMINATION SUR UN CÔTÉ ARRIÈRE D'UN SUBSTRAT SEMI-CONDUCTEUR
Abstract:
(EN) Techniques and mechanisms to mitigate contamination of redistribution layer structures disposed on a back side of a semiconductor substrate. In an embodiment, a microelectronics device includes a substrate and integrated circuitry variously formed in or on a front side of the substrate, where vias extend from the integrated circuitry to a back side of the substrate. A redistribution layer disposed on the back side includes a ring structure and a plurality of raised structures each extending from a recess portion that is surrounded by the ring structure. The ring structure and the plurality of raised structures provide contact surfaces for improved adhesion of dicing tape to the back side. In another embodiment, the plurality of raised structures includes dummification comprising dummy structures that are each electrically decoupled from any via extending through the substrate.
(FR) L'invention concerne des techniques et des mécanismes permettant d'atténuer la contamination de structures de couche de redistribution disposées sur un côté arrière d'un substrat semi-conducteur. Dans un mode de réalisation, un dispositif microélectronique comprend un substrat et un circuit intégré formé de diverses manières dans ou sur un côté avant du substrat, des trous d'interconnexion s'étendant du circuit intégré à un côté arrière du substrat. Une couche de redistribution disposée sur le côté arrière comprend une structure annulaire et une pluralité de structures surélevées s'étendant chacune à partir d'une partie renfoncée qui est entourée par la structure annulaire. La structure annulaire et la pluralité de structures surélevées fournissent des surfaces de contact pour améliorer l'adhérence d'une bande de découpage en dés sur le côté arrière. Dans un autre mode de réalisation, la pluralité de structures surélevées comprennent un simulacre comprenant des structures factices dont chacune est électriquement découplée de tout trou d'interconnexion s'étendant à travers le substrat.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)