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1. (WO2017112020) NON-CONTIGUOUS MULTIPLE REGISTER ACCESS FOR MICROPROCESSOR DATA EXCHANGE INSTRUCTIONS
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/112020 International Application No.: PCT/US2016/055225
Publication Date: 29.06.2017 International Filing Date: 03.10.2016
IPC:
G06F 15/80 (2006.01) ,G06F 9/30 (2006.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
15
Digital computers in general; Data processing equipment in general
76
Architectures of general purpose stored programme computers
80
comprising an array of processing units with common control, e.g. single instruction multiple data processors
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
9
Arrangements for programme control, e.g. control unit
06
using stored programme, i.e. using internal store of processing equipment to receive and retain programme
30
Arrangements for executing machine- instructions, e.g. instruction decode
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors:
GUO, Peng; CN
CHEN, Wei-Yu; US
LUEH, Guei-Yuan; US
MAIYURAN, Subramaniam; US
Agent:
AGHEVLI, Ramin; US
Priority Data:
14/976,78821.12.2015US
Title (EN) NON-CONTIGUOUS MULTIPLE REGISTER ACCESS FOR MICROPROCESSOR DATA EXCHANGE INSTRUCTIONS
(FR) ACCÈS À REGISTRES MULTIPLES NON CONTIGUS POUR INSTRUCTIONS D'ÉCHANGE DE DONNÉES DE MICROPROCESSEUR
Abstract:
(EN) Methods and apparatus relating to non-contiguous multiple register access for microprocessor data exchange instructions are described. In an embodiment, a plurality of registers store data. A processor exchanges the stored data between the one or more of the plurality of registers and a logic component in response to a single instruction. The plurality of registers are non-contiguous. Other embodiments are also disclosed and claimed.
(FR) L'invention concerne des procédés et un appareil concernant un accès à registres multiples non contigus pour des instructions d'échange de données de microprocesseur. Dans un mode de réalisation, une pluralité de registres stockent des données. Un processeur échange les données stockées entre le ou les registres de la pluralité de registres et un composant logique en réponse à une seule instruction. La pluralité de registres ne sont pas contigus. L'invention concerne également d'autres modes de réalisation.
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)