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1. (WO2017112014) THROUGH-MEMORY-LEVEL VIA STRUCTURES FOR A THREE-DIMENSIONAL MEMORY DEVICE
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/112014 International Application No.: PCT/US2016/054018
Publication Date: 29.06.2017 International Filing Date: 27.09.2016
IPC:
H01L 27/115
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
105
including field-effect components
112
Read-only memory structures
115
Electrically programmable read-only memories
Applicants:
SANDISK TECHNOLOGIES LLC [US/US]; Two Legacy Town Center 6900 North Dallas Parkway Plano, Texas 75024, US
Inventors:
TOYOMA, Fumiaki; US
MIZUTANI, Yuki; US
OGAWA, Hiroyuki; US
FURIHATA, Yoko; US
YU, Jixin; US
KAI, James; US
LIU, Jin; US
ALSMEIER, Johann; US
Agent:
RADOMSKY, Leon; US
BOUSHEHRI, Darjush; US
CONNOR, David; US
COHN, Joanna; US
DU, Albert; US
GAUL, Allison; US
GAYOSO, Tony; US
GILL, Matthew; US
HUANG, Stephen; US
HYAMS, David; US
HANSEN, Robert; US
JOHNSON, Timothy; US
LING, Yutian; US
MAZAHERY, Benjamin; US
MURPHY, Timothy; US
O'BRIEN, Michelle; US
PARK, Byeongju; US
ROBERTS, Jon; US
RUTT, Steven; US
SULSKY, Martin; US
SIMON, Phyllis; US
Priority Data:
15/268,94619.09.2016US
15/269,01719.09.2016US
15/269,04119.09.2016US
15/269,11219.09.2016US
15/269,29419.09.2016US
62/271,21022.12.2015US
Title (EN) THROUGH-MEMORY-LEVEL VIA STRUCTURES FOR A THREE-DIMENSIONAL MEMORY DEVICE
(FR) STRUCTURES DE TROUS DE LIAISON TRAVERSANT DES NIVEAUX DE MÉMOIRE POUR UN DISPOSITIF DE MÉMOIRE TRIDIMENSIONNEL
Abstract:
(EN) A three dimensional NAND memory device includes word line driver devices located on or over a substrate, an alternating stack of word lines and insulating layers located over the word line driver devices, a plurality of memory stack structures extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and through-memory-level via structures which electrically couple the word lines in a first memory block to the word line driver devices. The through-memory-level via structures extend through a through-memory-level via region located between a staircase region of the first memory block and a staircase region of another memory block.
(FR) Un dispositif mémoire NAND tridimensionnel comporte des dispositifs de commande de ligne de mot situés sur un substrat ou au-dessus de celui-ci, une pile alternée de lignes de mot et des couches isolantes situées au-dessus des dispositifs de commande de ligne de mot, une pluralité de structures de pile de mémoires s’étendant à travers la pile alternée, chaque structure de pile de mémoires comportant un film de mémoire et un canal semi-conducteur vertical, et des structures de trous de liaison traversant des niveaux de mémoire qui couplent électriquement les lignes de mot dans un premier bloc de mémoire aux dispositifs de commande de ligne de mot. Les structures de trous de liaison traversant des niveaux de mémoire s’étendent à travers à une région de trous de liaison traversant des niveaux de mémoire située entre une région en escalier du premier bloc de mémoire et une région en escalier d’un autre bloc de mémoire.
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
CN108377660KR1020180095499