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1. (WO2017111917) MICROELECTRONIC DEVICES WITH EMBEDDED SUBSTRATE CAVITIES FOR DEVICE TO DEVICE COMMUNICATIONS
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/111917 International Application No.: PCT/US2015/067184
Publication Date: 29.06.2017 International Filing Date: 21.12.2015
IPC:
H05K 1/02 (2006.01) ,H05K 1/18 (2006.01) ,H05K 3/46 (2006.01)
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1
Printed circuits
02
Details
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1
Printed circuits
18
Printed circuits structurally associated with non-printed electric components
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3
Apparatus or processes for manufacturing printed circuits
46
Manufacturing multi-layer circuits
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95052, US
Inventors:
NAIR, Vijay K.; US
OSTER, Sasha N.; US
ELSHERBINI, Adel A.; US
KAMGAING, Telesphor; US
EID, Feras; US
Agent:
BRASK, Justin, K.; US
Priority Data:
Title (EN) MICROELECTRONIC DEVICES WITH EMBEDDED SUBSTRATE CAVITIES FOR DEVICE TO DEVICE COMMUNICATIONS
(FR) DISPOSITIFS MICROÉLECTRONIQUES À CAVITÉS DE SUBSTRAT NOYÉES POUR COMMUNICATIONS DE DISPOSITIF À DISPOSITIF
Abstract:
(EN) Embodiments of the invention include a waveguide structure that includes a lower member, at least one sidewall member coupled to the lower member, and an upper member. The lower member, the at least one sidewall member, and the upper member include at least one conductive layer to form a cavity in a substrate for allowing communications between devices that are coupled or attached to the substrate.
(FR) Selon des modes de réalisation, l'invention concerne une structure de guide d'ondes qui comprend un élément inférieur, au moins un élément paroi latérale accouplé à l'élément inférieur, et un élément supérieur. L'élément inférieur, l'au moins un élément paroi latérale et l'élément supérieur comprennent au moins une couche conductrice pour former, dans un substrat, une cavité destinée à permettre des communications entre des dispositifs qui sont accouplés ou fixés au substrat.
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
DE112015007202US20180310399