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1. (WO2017111869) TRANSITION METAL DICHALCOGENIDES (TMDCS) OVER III-NITRIDE HETEROEPITAXIAL LAYERS
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CLAIMS

What is claimed is:

1. A heteroepitaxial structure, comprising:

a substrate comprising silicon;

a crystalline III-N material disposed over the silicon; and

a crystalline transition metal dichalcogenide (TMDC) layer disposed over the III-N material.

2. The structure of claim 1 , wherein at least a portion of a III-N layer in direct contact with the TMDC has a lattice constant matching to within 1 % that of the TMDC layer.

3. The structure of claim 2, wherein the III-N material includes:

a A1N nucleation layer disposed over the silicon;

an intermediate layer disposed over the nucleation layer, the intermediate layer comprising a III-N material having a bandgap at least equal to that of GaN and a film thickness greater than that of the nucleation layer; and

a seeding surface layer comprising a III-N material with the lattice constant matching that of the TMDC layer.

4. The structure of claim 1 , further comprising impurity-doped III-N material in contact with a portion of the TMDC layer.

5. The structure of claim 4, further comprising:

an impurity-doped III-N source material disposed in contact with a first portion of the

TMDC layer; and

an impurity-doped III-N drain material in contact with a second portion of the TMDC layer.

6. The structure of claim 5, wherein the first portion of the TMDC layer overlaps the III-N source material and the second portion of the TMDC layer overlaps the III-N drain material.

7. The structure of claim 6, wherein:

the doped III-N source material is disposed on the first portion of the TMDC layer; and

the doped III-N drain material is disposed on the second portion of the TMDC layer.

8. The structure of claim 1 , wherein:

the transition metal comprises at least one of W, Mo, and Hf;

the chalcogen comprises at least one of S, Se, and Te;

the TMDC layer comprises an odd number of crystal monolayers disposed over the III-N material;

the c-axis of the TMDC layer is substantially aligned with the c-axis of the III-N material; and

the III-N material is disposed on a (100) surface of the silicon.

9. The structure of claim 1, wherein the III-N material interfaces with the silicon at a bottom of a trench defined by an amorphous material disposed over a portion of the silicon, and the III-N material extends laterally over the amorphous material.

10. The structure of claim 1 , wherein:

the TMDC layer is disposed over a first region of the substrate; and

the structure further comprises a III-N polarization material disposed over the III-N material over a second region of the substrate adjacent to the first region.

1 1. The structure of claim 10, wherein:

the structure further comprises a (100) silicon surface over a third region of the substrate adjacent to at least one of the first region or second region.

12. The structure of claim 1 1 , wherein within the second substrate region the III-N material is disposed on a (1 1 1 ) surface of the silicon, and within the third substrate region a dielectric layer is disposed between the (100) silicon surface and the (1 1 1 ) surface of the silicon.

13. The structure of claim 1 , further comprising:

a gate stack disposed on a portion of the TMDC layer;

contact metallization coupled to first and second portions of the TMDC layer disposed on opposite sides of the gate stack; and

impurity doped III-N source/drain material disposed between the contact metallization and the first and second portions of the TMDC layer.

14. A monolithic integrated circuit (IC), comprising:

a substrate comprising:

a silicon crystal;

a III-N crystal disposed over the silicon crystal; and

a transition metal dichalcogenide (TMDC) crystal disposed on the III-N crystal; and a first semiconductor device including at least one terminal coupled to the TMDC crystal.

15. the IC of claim 14, further comprising a second semiconductor device including at least one terminal coupled to a first of the III-N crystal or the silicon crystal.

16. The IC of claim 15, wherein:

the first semiconductor device comprises a first transistor including at least three first terminals coupled to the TMDC crystal;

the first terminals include a first gate electrode disposed over a channel portion of the

TMDC crystal;

the second semiconductor device comprises a second transistor including at least three second terminals coupled to the III-N crystal; and

the second terminals include a second gate electrode disposed over a channel portion of the

III-N crystal.

17. The IC of claim 16, wherein the first terminals include a pair of source/drain

metallizations coupled to the TMDC crystal through impurity-doped III-N material disposed on opposite sides of the first gate electrode.

18. The IC of claim 14, further comprising a third semiconductor device including at least one terminal coupled to a second of the III-N crystal or the silicon crystal.

19. A method of fabricating a transition metal dichalcogenide (TMDC) device, the method comprising:

receiving a substrate including a III-N crystal;

epitaxial ly forming a TMDC crystal over a surface of the III-N crystal; and

forming device terminals coupled to the TMDC crystal.

20. The method of claim 19, wherein:

a surface of the III-N crystal is lattice matched to that of the TMDC crystal to within 1 %; the TMDC crystal comprises an odd number of crystal monolayers disposed over the III-N crystal;

the c-axis of the TMDC crystal is substantially aligned with the c-axis of the III-N crystal; and

the III-N crystal is disposed on a silicon crystal.

21. The method of claim 19, wherein:

the TMDC device is a transistor;

the method further comprises epitaxially forming impurity-doped III-N source/drain material contacting first and second portions of the TMDC crystal; and

forming the device terminals further comprises:

fabricating a gate stack over the TMDC crystal between the first and second portions; and

depositing metallization on the impurity-doped III-N source/drain material.

22. The method of claim 19, further comprising:

forming an amorphous material over first portions of a silicon region of the substrate;

forming trenches in the amorphous material exposing a seeding surface of the silicon region; and

growing the III-N crystal from the seeding surface and laterally over the amorphous

material.

23. The method of claim 22, wherein:

the method further comprises growing an impurity-doped III-N material over a portion of the III-N crystal to contact portions of the TMDC crystal.

24. The method of claim 23, wherein growing the impurity-doped III-N material comprises laterally overgrowing the impurity-doped III-N material from the III-N crystal.

25. The method of claim 19,wherein:

epitaxially forming the TMDC crystal over a surface of the III-N crystal further comprises growing a TMDC crystal monolayer over a first III-N crystal surface;

the method further comprises epitaxialiy forming a III-N polarization layer over a second

III-N crystal surface; and

forming the device terminals further comprises:

fabricating a first gate stack over the TMDC crystal and a second gate stack of the

III-N polarization layer; and

depositing metallization on impurity-doped III-N source/drain material disposed on the TMDC crystal and at least the second III-N crystal surface.

26. The method of claim 25, wherein:

only a first portion of the substrate is covered by the III-N crystal and a second portion of the substrate comprises a (100) silicon surface; and

the method further comprises forming a silicon transistor of the (100) silicon surface.