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1. (WO2017111854) METHODS OF FORMING LOW CAPACITANCE INTERCONNECT STRUCTURES UTILIZING LOW DIELECTRIC MATERIALS
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/111854 International Application No.: PCT/US2015/000428
Publication Date: 29.06.2017 International Filing Date: 24.12.2015
IPC:
H01L 21/768 (2006.01) ,H01L 21/205 (2006.01) ,H01L 21/31 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
768
Applying interconnections to be used for carrying current between separate components within a device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
20
Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
205
using reduction or decomposition of a gaseous compound yielding a solid condensate, i.e. chemical deposition
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, CA 95054, US
Inventors:
CHANDHOK, Mainish; US
LIAO, Szuya; US
YOO, Hui, Jae; US
BINDL, Sominick; US
CHAO, Huang-lin; US
TURKOT, Robert; US
KAVALIEROS, Jack; US
Agent:
ORTIZ, Kathy; US
Priority Data:
Title (EN) METHODS OF FORMING LOW CAPACITANCE INTERCONNECT STRUCTURES UTILIZING LOW DIELECTRIC MATERIALS
(FR) PROCÉDÉS DE FORMATION DE STRUCTURES D'INTERCONNEXION À FAIBLE CAPACITÉ UTILISANT DES MATIÈRES DIÉLECTRIQUES FAIBLES
Abstract:
(EN) Methods of lowering the capacitance of interconnect patterns comprising adjacent metal lines with differing metal compositions, are described. Those methods/structures may include providing a substrate comprising a first conductive interconnect structure comprising a first material, and a second interconnect structure comprising a second material, wherein the first and second conductive interconnect structures are disposed adjacent to one another on the substrate, forming an air gap disposed between the first and second conductive interconnect structures by utilizing a vapor phase etch process, and encapsulating the air gap with a low k dielectric material.
(FR) La présente invention porte sur des procédés d'abaissement de la capacité de motifs d'interconnexion comprenant des lignes métalliques adjacentes avec différentes compositions métalliques. Ces procédés/structures peuvent comprendre la fourniture d'un substrat comprenant une première structure d'interconnexion conductrice comprenant une première matière, et une seconde structure d'interconnexion comprenant une seconde matière, les première et seconde structures d'interconnexion conductrices étant disposées adjacentes les unes aux autres sur le substrat, formant un entrefer disposé entre les première et seconde structures d'interconnexion conductrices au moyen d'un procédé de gravure en phase vapeur, et encapsulant l'entrefer avec la matière diélectrique à faible k.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)