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1. (WO2017111838) VERTICALLY EMBEDDED PASSIVE COMPONENTS
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/111838 International Application No.: PCT/US2015/000396
Publication Date: 29.06.2017 International Filing Date: 26.12.2015
IPC:
H01L 23/48 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, CA 95054, US
Inventors:
LAMBERT, William, J.; US
ROY, Mihir, K.; US
MANUSHAROW, Mathew, J.; US
Agent:
BRASK, Justin, K.; US
Priority Data:
Title (EN) VERTICALLY EMBEDDED PASSIVE COMPONENTS
(FR) COMPOSANTS PASSIFS INTÉGRÉS VERTICALEMENT
Abstract:
(EN) Embodiments are generally directed to vertically embedded passive components. An embodiment of a device includes a semiconductor die; and a package coupled with the semiconductor die. The package includes one or more passive components connected with the semiconductor die, the one or more passive components being embedded vertically in the package substrate, each of the passive components including a first terminal and a second terminal. A first passive component is embedded in a through hole drilled in the package, the first terminal of the first passive component being connected to the semiconductor die by a via through an upper buildup layer on the package.
(FR) Des modes de réalisation ont trait en général à des composants passifs intégrés verticalement. Un mode de réalisation d'un dispositif comporte une puce semi-conductrice et un boîtier couplé à la puce semi-conductrice. Le boîtier comporte un ou plusieurs composants passifs connectés à la puce semi-conductrice, le ou les composants passifs étant intégrés verticalement dans le substrat du boîtier et chaque composant passif comporte une première borne et une seconde borne. Un premier composant passif est intégré dans un trou débouchant percé dans le boîtier, la première borne du premier composant passif étant connectée à la puce semi-conductrice par un trou de liaison à travers une couche constituante supérieure sur le boîtier.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
CN108292641DE112015007240US20180332708