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1. (WO2017111825) HYBRID TECHNOLOGY 3-D DIE STACKING
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/111825 International Application No.: PCT/US2015/000383
Publication Date: 29.06.2017 International Filing Date: 26.12.2015
IPC:
H01L 25/16 (2006.01) ,H01L 23/48 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
16
the devices being of types provided for in two or more different main groups of groups H01L27/-H01L51/139
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, CA 95054, US
Inventors:
SARKAR, Arnab; US
MAHAJAN, Ravindranath, V.; US
Agent:
BRASK, Justin, K.; US
Priority Data:
Title (EN) HYBRID TECHNOLOGY 3-D DIE STACKING
(FR) EMPILEMENT DE PUCES 3D À TECHNOLOGIE HYBRIDE
Abstract:
(EN) Embodiments are generally directed to hybrid technology 3-D die stacking. An embodiment of an apparatus includes a TSV array substrate including through silicon vias (TSVs) and wire bond contacts; a stack of one or more wire bond dies; and a package coupled with the TSV substrate by a first interconnect, wherein the one or more wire bond dies are connected via one or more wires to one or more wire bond contacts of the TSV array substrate, and wherein the TSV array substrate provides connections to the for each of the one or more wire bond dies.
(FR) Des modes de réalisation concernent généralement l'empilement de puces 3D à technologie hybride. Un mode de réalisation d'un appareil comprend un substrat de matrice de TSV comprenant des vias traversants (TSV) et des contacts à connexion par fil; un empilement d'une ou de plusieurs puces de connexion par fil; et un boîtier couplé au substrat TSV par une première interconnexion, la ou les puces de connexion par fil étant connectées au moyen d'un ou de plusieurs fils à un ou plusieurs contacts à connexion par fil du substrat de matrice TSV et le substrat de matrice TSV fournissant des connexions à chacune de la ou des puces de connexion par fil.
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
DE112015007236