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1. (WO2017111820) REDUCED HEIGHT LINER FOR INTERCONNECTS
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/111820 International Application No.: PCT/US2015/000378
Publication Date: 29.06.2017 International Filing Date: 26.12.2015
IPC:
H01L 21/768 (2006.01) ,H01L 21/60 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
768
Applying interconnections to be used for carrying current between separate components within a device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
60
Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors:
CHOWDHURY, Akm Shaestagir; US
GRIGGIO, Flavio; US
Agent:
RICHARDS, II, E.E. "Jack"; US
Priority Data:
Title (EN) REDUCED HEIGHT LINER FOR INTERCONNECTS
(FR) REVÊTEMENT À HAUTEUR RÉDUITE POUR DES INTERCONNEXIONS
Abstract:
(EN) An embodiment includes a metal interconnect structure, comprising: a dielectric layer on a substrate; an opening, in the dielectric layer, (a) having sidewalls and an aspect ratio of at least 5:1 (height: width), and (b) exposing a conductive region of at least one of the substrate and an additional interconnect structure; a conformal thin film layer on the sidewalls; and a polycrystalline metal within the opening and on the thin film layer; wherein the thin film layer forms an adhesive liner that extends only partially up the sidewalls leaving upper portions of the sidewalls uncovered by the liner. Other embodiments are described herein.
(FR) La présente invention concerne, dans un mode de réalisation, une structure d'interconnexion métallique, comprenant : une couche diélectrique sur un substrat ; une ouverture, dans la couche diélectrique, (a) ayant des parois latérales et un rapport d'aspect d'au moins 5:1 (hauteur:largeur), et (b) exposant une région conductrice d'au moins l'un du substrat et d'une structure d'interconnexion supplémentaire ; une couche de film mince conforme sur les parois latérales ; et un métal polycristallin dans l'ouverture et sur la couche de film mince ; la couche de film mince formant un revêtement adhésif qui s'étend seulement partiellement vers le haut des parois latérales, laissant des parties supérieures des parois latérales découvertes par le revêtement. L'invention porte également sur d'autres modes de réalisation.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)