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1. (WO2017111804) STRUCTURE FOR IMPROVED SHORTING MARGIN AND TIME DEPENDENT DIELECTRIC BREAKDOWN IN INTERCONNECT STRUCTURES
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/111804 International Application No.: PCT/US2015/000345
Publication Date: 29.06.2017 International Filing Date: 24.12.2015
IPC:
H01L 21/768 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
768
Applying interconnections to be used for carrying current between separate components within a device
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, CA 95054, US
Inventors:
KOBRINSKY, Mauro, J.; US
CLARKE, James, S.; US
SINGH, Kanwal, J.; US
BOYANOV, Boyan; US
MYERS, Alan, M.; US
Agent:
BRASK, Justin, K.; US
Priority Data:
Title (EN) STRUCTURE FOR IMPROVED SHORTING MARGIN AND TIME DEPENDENT DIELECTRIC BREAKDOWN IN INTERCONNECT STRUCTURES
(FR) STRUCTURE POUR MARGE DE COURT-CIRCUIT AMÉLIORÉE ET RUPTURE DIÉLECTRIQUE EN FONCTION DU TEMPS DANS DES STRUCTURES D'INTERCONNEXION
Abstract:
(EN) A method including forming a dielectric layer on a contact point on a device substrate; forming a barrier layer on the dielectric layer; forming a contact through the dielectric layer and the barrier layer to the contact point; recessing the contact relative to a thickness of the barrier layer; conformally forming a passivation layer on the contact and barrier layer; and forming an opening to the contact. An apparatus including an integrated circuit substrate including a device layer including a plurality of devices; a dielectric layer on the device layer; a barrier layer on the dielectric layer; a first contact through the dielectric layer and the barrier layer to a contact point of the device layer; a passivation layer on the barrier layer; and a second contact disposed through the passivation layer and the barrier layer and coupled to the first contact.
(FR) L'invention concerne un procédé consistant à former une couche diélectrique sur un point de contact sur un dispositif de substrat; former une couche barrière sur la couche diélectrique; former un contact à travers la couche diélectrique et la couche barrière jusqu'au point de contact; évider le contact par rapport à une épaisseur de la couche barrière; former par conformation une couche de passivation sur le contact et la couche barrière; et former une ouverture vers le contact. L'invention concerne également un appareil contenant un substrat à circuit intégré contenant une couche de dispositifs contenant une pluralité de dispositifs; une couche diélectrique sur la couche de dispositifs; une couche barrière sur la couche diélectrique; un premier contact à travers la couche diélectrique et la couche barrière jusqu'à un point de contact de la couche de dispositifs; une couche de passivation sur la couche barrière; et un second contact disposé à travers la couche de passivation et la couche barrière et couplé au premier contact.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)