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1. (WO2017111795) MULTIPLE STACKED FIELD-PLATED GAN TRANSISTOR AND INTERLAYER DIELECTRICS TO IMPROVE BREAKDOWN VOLTAGE AND REDUCE PARASITIC CAPACITANCES
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/111795 International Application No.: PCT/US2015/000317
Publication Date: 29.06.2017 International Filing Date: 23.12.2015
IPC:
H01L 29/78 (2006.01) ,H01L 21/336 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, CA 95054, US
Inventors:
THEN, Han, Wui; US
DASGUPTA, Sansaptak; US
RADOSAVLJEVIC, Marko; US
GARDNER, Sanaz, K.; US
SUNG, Seung, Hoon; US
Agent:
BRASK, Justin, K.; US
Priority Data:
Title (EN) MULTIPLE STACKED FIELD-PLATED GAN TRANSISTOR AND INTERLAYER DIELECTRICS TO IMPROVE BREAKDOWN VOLTAGE AND REDUCE PARASITIC CAPACITANCES
(FR) TRANSISTOR AU GAN À MULTIPLES PLAQUES DE CHAMP EMPILÉES ET DIÉLECTRIQUES INTERCOUCHES POUR AMÉLIORER LA TENSION DE CLAQUAGE ET RÉDUIRE LES CAPACITÉS PARASITES
Abstract:
(EN) Embodiments of the invention include a high voltage transistor with one or more field plates and methods of forming such transistors. According to an embodiment, the transistor may include a source region, a drain region, and a gate electrode formed over a channel region formed between the source region and drain region. Embodiments of the invention may also include a first interlayer dielectric (ILD) formed over the channel region and a second ILD formed over the first ILD. According to an embodiment, a first field plate may be formed in the second ILD. In an embodiment the first field plate is not formed as a single bulk conductive feature with the gate electrode. In some embodiments, the first field plate may be electrically coupled to the gate electrode by one or more vias. In alternative embodiments, the first field plate may be electrically isolated from the gate electrode.
(FR) La présente invention concerne, dans certains modes de réalisation, un transistor haute tension pourvu d'une ou de plusieurs plaques de champ et des procédés de formation de tels transistors. Selon un mode de réalisation, le transistor peut comprendre une région de source, une région de drain, et une électrode de grille formée sur une région de canal formée entre la région de source et la région de drain. Des modes de réalisation de l'invention peuvent également comprendre un premier diélectrique intercouche (ILD) formé sur la région de canal et un second ILD formé sur le premier ILD. Selon un mode de réalisation, une première plaque de champ peut être formée dans le second ILD. Dans un mode de réalisation, la première plaque de champ n'est pas formée sous la forme d'un unique élément à conductivité volumique avec l'électrode de grille. Dans certains modes de réalisation, la première plaque de champ peut être couplée électriquement à l'électrode de grille par un ou plusieurs trous d'interconnexion. Dans d'autres modes de réalisation, la première plaque de champ peut être isolée électriquement de l'électrode de grille.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
US20180331191