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1. (WO2017110723) DIPLEXER CIRCUIT AND DIPLEXER CIRCUIT MODULE
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/110723 International Application No.: PCT/JP2016/087736
Publication Date: 29.06.2017 International Filing Date: 19.12.2016
IPC:
H03H 7/46 (2006.01) ,H04B 1/50 (2006.01)
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
H
IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
7
Multiple-port networks comprising only passive electrical elements as network components
46
Networks for connecting several sources or loads, working on different frequencies or frequency bands, to a common load or source
H ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
B
TRANSMISSION
1
Details of transmission systems, not covered by a single one of groups H04B3/-H04B13/123; Details of transmission systems not characterised by the medium used for transmission
38
Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
40
Circuits
50
using different frequencies for the two directions of communication
Applicants:
株式会社村田製作所 MURATA MANUFACTURING CO., LTD. [JP/JP]; 京都府長岡京市東神足1丁目10番1号 10-1, Higashikotari 1-chome, Nagaokakyo-shi, Kyoto 6178555, JP
Inventors:
鷲森 直史 WASHIMORI, Tadashi; JP
吉田 正人 YOSHIDA, Masato; JP
Agent:
河本 尚志 KAWAMOTO, Takashi; JP
Priority Data:
2015-25337825.12.2015JP
Title (EN) DIPLEXER CIRCUIT AND DIPLEXER CIRCUIT MODULE
(FR) CIRCUIT DIPLEXEUR ET MODULE DE CIRCUIT DIPLEXEUR
(JA) ダイプレクサ回路およびダイプレクサ回路モジュール
Abstract:
(EN) Provided is a diplexer circuit in which unnecessary attenuation occurring in a pass band of a high-pass filter (or a band-pass filter) is inhibited. The present invention is provided with: a shared terminal X; a transmission terminal Y; a reception terminal Z; a diplexer DPLX which is equipped with a first terminal T1, a second terminal T2, a third terminal T3, a first low-pass filter LPF1, and a high-pass filter HPF (or a band-pass filter BPF); a second low-pass filter LPF2; a third low-pass filter LPF3; and a first switch SW1 and a second switch SW2 that are switched in a linked manner, wherein the configuration of switching the first switch SW1 and the second switch SW2 in a linked manner enables, either the second low-pass filter LPF2 or the third low-pass filter LPF3 to be alternatively connected between the first switch SW1 and the second switch SW2.
(FR) L’invention concerne un circuit diplexeur dans lequel une atténuation inutile dans une bande passante d’un filtre passe-haut (ou un filtre passe-bande) est inhibée. La présente invention comporte : une borne partagée (X) ; une borne de transmission (Y) ; une borne de réception (Z) ; un diplexeur (DPLX) qui est équipé d’une première borne (T1), d’une deuxième borne (T2), d’une troisième borne (T3), d’un premier filtre passe-bas (LPF1), et d’un filtre passe-haut (HPF) (ou d’un filtre passe-bande (BPF)) ; un deuxième filtre passe-bas (LPF2) ; un troisième filtre passe-bas (LPF3) ; et un premier commutateur (SW1) et un deuxième commutateur (SW2) qui sont commutés de manière liée, la configuration de commutation du premier commutateur (SW1) et du deuxième commutateur (SW2) de manière liée permet que le deuxième filtre passe-bas (LPF2) ou le troisième filtre passe-bas (LPF3) soit alternativement connecté entre le premier commutateur (SW1) et le deuxième commutateur (SW2).
(JA) ハイパスフィルタ(またはバンドパスフィルタ)の通過帯域内に発生する不要な減衰が抑制されたダイプレクサ回路を提供する。 共用端子Xと、送信端子Yと、受信端子Zと、ダイプレクサDPLXであって、第1端子T1と、第2端子T2と、第3端子T3と、第1ローパスフィルタLPF1と、ハイパスフィルタHPF(またはバンドパスフィルタBPF)とを備えたものと、第2ローパスフィルタLPF2と、第3ローパスフィルタLPF3と、連動して切り替えられる第1スイッチSW1および第2スイッチSW2と、を備え、第1スイッチSW1および第2スイッチSW2を連動して切り替えることにより、第2ローパスフィルタLPF2および第3ローパスフィルタLPF3のいずれか一方が、第1スイッチSW1と第2スイッチSW2との間に択一的に接続されるようにした。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)