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1. (WO2017110006) SEMICONDUCTOR DEVICE
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/110006 International Application No.: PCT/JP2015/086451
Publication Date: 29.06.2017 International Filing Date: 26.12.2015
IPC:
H01L 21/331 (2006.01) ,H01L 29/732 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
328
Multistep processes for the manufacture of devices of the bipolar type, e.g. diodes, transistors, thyristors
33
the devices comprising three or more electrodes
331
Transistors
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
70
Bipolar devices
72
Transistor-type devices, i.e. able to continuously respond to applied control signals
73
Bipolar junction transistors
732
Vertical transistors
Applicants:
新電元工業株式会社 SHINDENGEN ELECTRIC MANUFACTURING CO., LTD. [JP/JP]; 東京都千代田区大手町二丁目2番1号 2-1, Ohtemachi 2-chome, Chiyoda-ku, Tokyo 1000004, JP
Inventors:
清水 隆史 SHIMIZU, Takashi; JP
園部 朋子 SONOBE, Tomoko; JP
安孫子 倫生 ABIKO, Michio; JP
Agent:
松尾 誠剛 MATSUO, Nobutaka; JP
Priority Data:
Title (EN) SEMICONDUCTOR DEVICE
(FR) DISPOSITIF À SEMI-CONDUCTEUR
(JA) 半導体装置
Abstract:
(EN) A semiconductor device 100 provided with a base layer 116, an emitter region 118 formed on a prescribed region of the surface of the base layer, a collector layer 120 formed on a region surrounding the emitter region, and a base contact region 124 formed on a prescribed region of the region surrounding the collector layer, a bipolar transistor being configured by the base layer, the emitter region, and the collector layer, wherein the collector layer has a depth reaching near the bottom surface of the base layer, and has a prescribed gap D along the circumferential direction of the collector layer. According to this semiconductor device 100, when a prescribed collector voltage VCE is applied, the gap D assumes a pinched-off state by a depletion layer that expands from the collector layer toward the base layer. As a result, a collector current IC is blocked before the collector voltage VCE reaches the rated voltage of the bipolar transistor, and thermal destruction occurs less easily than in the past.
(FR) L'invention porte sur un dispositif à semi-conducteur (100) qui comprend une couche de base (116), une zone d'émetteur (118) formée sur une zone prescrite de la surface de la couche de base, une couche de collecteur (120) formée sur une zone entourant la zone d'émetteur, et une zone de contact de base (124) formée sur une zone prescrite de la zone entourant la couche de collecteur, un transistor bipolaire étant configuré par la couche de base, la zone d'émetteur et la couche de collecteur, la couche de collecteur ayant une profondeur atteignant presque la surface inférieure de la couche de base, et comportant un espacement prescrit D le long de la direction circonférentielle de la couche de collecteur. Selon ce dispositif à semi-conducteur (100), lorsqu'une tension de collecteur VCE prescrite est appliquée, l'espacement D prend un état pincé par une couche d'appauvrissement qui se dilate de la couche de collecteur vers la couche de base. En conséquence, un courant de collecteur IC est bloqué avant que la tension de collecteur VCE atteigne la tension nominale du transistor bipolaire, et une destruction thermique survient moins facilement que dans le passé.
(JA) ベース層116と、ベース層の表面所定領域に形成されてなるエミッタ領域118と、エミッタ領域を取り囲む領域に形成されてなるコレクタ層120と、コレクタ層を取り囲む領域の所定領域に形成されてなるベースコンタクト領域124とを備え、ベース層、エミッタ領域及びコレクタ層によりバイポーラトランジスタが構成されてなる半導体装置であって、コレクタ層は、ベース層の底面近傍に達する深さを有し、かつ、コレクタ層の周方向に沿った所定の隙間Dを有する半導体装置100。 本発明の半導体装置100によれば、所定のコレクタ電圧VCEが印加されると、コレクタ層からベース層に向かって伸張する空乏層によって隙間Dがピンチオフ状態となる結果、コレクタ電圧VCEがバイポーラトランジスタの定格電圧に達する前にコレクタ電流Iが遮断されるようになり、従来よりも、熱破壊が起こり難くなる。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)
Also published as:
JPWO2017110006