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1. (WO2017099897) DIGITAL AGGREGATION OF INTERRUPTS FROM PERIPHERAL DEVICES
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/099897 International Application No.: PCT/US2016/058715
Publication Date: 15.06.2017 International Filing Date: 25.10.2016
Chapter 2 Demand Filed: 20.09.2017
IPC:
G06F 13/24 (2006.01) ,H03M 1/78 (2006.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
13
Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14
Handling requests for interconnection or transfer
20
for access to input/output bus
24
using interrupt
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
M
CODING, DECODING OR CODE CONVERSION, IN GENERAL
1
Analogue/digital conversion; Digital/analogue conversion
66
Digital/analogue converters
74
Simultaneous conversion
78
using ladder network
Applicants:
QUALCOMM INCORPORATED [US/US]; ATTN: International IP Administration 5775 Morehouse Drive San Diego, California 92121-1714, US
Inventors:
MISHRA, Lalan Jee; US
WIETFELDT, Richard Dominic; US
SHAH, Peter; US
Agent:
HALLMAN, Jonathan W.; US
Priority Data:
14/965,51110.12.2015US
Title (EN) DIGITAL AGGREGATION OF INTERRUPTS FROM PERIPHERAL DEVICES
(FR) AGRÉGATION NUMÉRIQUE D'INTERRUPTIONS PROVENANT DE DISPOSITIFS PÉRIPHÉRIQUES
Abstract:
(EN) A host integrated circuit (101) is provided with an interrupt aggregator having a signal terminal for coupling to the signal end of an R-2R resistor ladder (102) that has a plurality of rungs corresponding to a plurality of peripheral devices. The interrupt aggregator is configured to process a voltage signal received at the signal terminal to identify any of the peripheral device that intend to trigger an interrupt to a processor.
(FR) L'invention concerne un circuit intégré hôte (101) muni d'un agrégateur d'interruptions doté d'une borne de signal destinée à se coupler à l'extrémité de signal d'une échelle (102) de résistances R-2R qui comprend une pluralité d'échelons correspondant à une pluralité de dispositifs périphériques. L'agrégateur d'interruptions est configuré pour traiter un signal de tension reçu au niveau de la borne de signal afin d'identifier parmi les dispositifs périphériques un éventuel dispositif s'apprêtant à déclencher une interruption vers un processeur.
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
AU2016369231IN201847016567CN108369564KR1020180090999EP3387538ID2018/12162
BR112018011601