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1. (WO2017099096) SEMICONDUCTOR APPARATUS
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/099096 International Application No.: PCT/JP2016/086285
Publication Date: 15.06.2017 International Filing Date: 06.12.2016
IPC:
H01L 29/739 (2006.01) ,H01L 29/12 (2006.01) ,H01L 29/78 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
70
Bipolar devices
72
Transistor-type devices, i.e. able to continuously respond to applied control signals
739
controlled by field effect
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
12
characterised by the materials of which they are formed
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
Applicants:
富士電機株式会社 FUJI ELECTRIC CO., LTD. [JP/JP]; 神奈川県川崎市川崎区田辺新田1番1号 1-1, Tanabeshinden, Kawasaki-ku, Kawasaki-shi, Kanagawa 2109530, JP
Inventors:
内藤 達也 NAITO Tatsuya; JP
Agent:
龍華国際特許業務法人 RYUKA IP LAW FIRM; 東京都新宿区西新宿1-6-1 新宿エルタワー22階 22F, Shinjuku L Tower, 1-6-1, Nishi-Shinjuku, Shinjuku-ku, Tokyo 1631522, JP
Priority Data:
2015-24247411.12.2015JP
2016-15892012.08.2016JP
Title (EN) SEMICONDUCTOR APPARATUS
(FR) APPAREIL SEMI-CONDUCTEUR
(JA) 半導体装置
Abstract:
(EN) The present invention addresses the problem of a trench being formed deeper at a gate trench branching portion than at a linear gate trench portion. Provided is a semiconductor apparatus comprising: a first conductivity-type semiconductor substrate; a second conductivity-type base region disposed on an upper surface side of the semiconductor substrate; a first trench portion disposed penetrating through the base region from the upper surface of the semiconductor substrate; and a second conductivity-type contact region which is disposed in a part of the base region on the upper surface side of the semiconductor substrate, and which has a higher impurity concentration than the base region, wherein the first trench portion includes a branch portion on the upper surface of the semiconductor substrate, the branch portion being surrounded by the contact region on the upper surface of the semiconductor substrate.
(FR) La présente invention traite le problème de la formation d'une tranchée plus profonde au niveau d'une partie ramification de tranchée de grille qu'au niveau d'une partie tranchée de grille linéaire. L'invention concerne un appareil semi-conducteur comprenant : un substrat semi-conducteur d'un premier type de conductivité ; une région de base d'un deuxième type de conductivité disposée sur un côté surface supérieure du substrat semi-conducteur ; une première partie tranchée traversant la région de base à partir de la surface supérieure du substrat semi-conducteur ; et une région de contact d'un deuxième type de conductivité, disposée dans une partie de la région de base sur le côté surface supérieure du substrat semi-conducteur, et qui présente une concentration d'impuretés supérieure à celle de la région de base, la première partie tranchée comprenant une portion ramification sur la surface supérieure du substrat semi-conducteur, la partie ramification étant entourée par la région de contact sur la surface supérieure du substrat semi-conducteur.
(JA) ゲートトレンチが分岐した部分では、直線状のゲートトレンチの部分よりも、トレンチが深く形成されてしまう。第1導電型の半導体基板と、半導体基板のおもて面側に設けられた第2導電型のベース領域と、半導体基板のおもて面からベース領域を貫通して設けられた第1トレンチ部と、半導体基板のおもて面側においてベース領域の一部に設けられ、ベース領域よりも不純物濃度の高い第2導電型のコンタクト領域とを備え、第1トレンチ部は、半導体基板のおもて面において分岐部を有し、分岐部は、半導体基板のおもて面においてコンタクト領域に囲まれて設けられる半導体装置を提供する。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)
Also published as:
CN107636836JPWO2017099096