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1. (WO2017099095) SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/099095 International Application No.: PCT/JP2016/086284
Publication Date: 15.06.2017 International Filing Date: 06.12.2016
IPC:
H01L 29/739 (2006.01) ,H01L 21/336 (2006.01) ,H01L 27/04 (2006.01) ,H01L 29/78 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
70
Bipolar devices
72
Transistor-type devices, i.e. able to continuously respond to applied control signals
739
controlled by field effect
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
Applicants:
富士電機株式会社 FUJI ELECTRIC CO., LTD. [JP/JP]; 神奈川県川崎市川崎区田辺新田1番1号 1-1, Tanabeshinden, Kawasaki-ku, Kawasaki-shi, Kanagawa 2109530, JP
Inventors:
内藤 達也 NAITO Tatsuya; JP
Agent:
龍華国際特許業務法人 RYUKA IP LAW FIRM; 東京都新宿区西新宿1-6-1 新宿エルタワー22階 22F, Shinjuku L Tower, 1-6-1, Nishi-Shinjuku, Shinjuku-ku, Tokyo 1631522, JP
Priority Data:
2015-24175711.12.2015JP
2016-18001114.09.2016JP
Title (EN) SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD
(FR) DISPOSITIF À SEMI-CONDUCTEUR ET PROCÉDÉ DE FABRICATION
(JA) 半導体装置および製造方法
Abstract:
(EN) The present invention both ensures a channel formation region and suppresses latch-up. Provided is a semiconductor device comprising: a semiconductor substrate; a plurality of trench parts which are disposed on the front face of the semiconductor substrate and which each have a portion the extends in an extension direction; and an emitter region of a first conduction type and a contact region of a second conduction type, which are disposed between two adjacent trench parts and which are alternately exposed in the extension direction on the front face of the semiconductor substrate. On the front face of the semiconductor substrate, the length of the emitter region at a center position between two trench parts is shorter than the length of the emitter region in a portion in contact with a trench part. At least a portion of the boundary of the emitter region is curved, on the front face of the semiconductor substrate.
(FR) La présente invention à la fois assure une région de formation de canal et empêche un déclenchement parasite. La présente invention porte sur un dispositif à semi-conducteur comprenant : un substrat semi-conducteur ; une pluralité de parties de tranchée qui sont disposées sur la face avant du substrat semi-conducteur et qui comportent chacune une partie qui s'étend dans une direction d'extension ; et une région émettrice d'un premier type de conduction et une région de contact d'un second type de conduction, qui sont disposées entre deux parties de tranchée adjacentes et qui sont exposées de manière alternée dans la direction d'extension sur la face avant du substrat semi-conducteur. Sur la face avant du substrat semi-conducteur, la longueur de la région émettrice à une position centrale entre deux parties de tranchée est plus courte que la longueur de la région émettrice dans une partie en contact avec une partie de tranchée. Au moins une partie de la frontière de la région émettrice est incurvée, sur la face avant du substrat semi-conducteur.
(JA) チャネル形成領域の確保と、ラッチアップ抑制を両立させる。半導体基板と、半導体基板のおもて面側に設けられ、それぞれが延伸方向に延伸する部分を有する複数のトレンチ部と、隣接する2つのトレンチ部の間に設けられ、延伸方向において交互に半導体基板のおもて面に露出する第1導電型のエミッタ領域および第2導電型のコンタクト領域とを備え、半導体基板のおもて面において、2つのトレンチ部の間の中央位置におけるエミッタ領域の長さは、トレンチ部に接する部分におけるエミッタ領域の長さよりも短く、半導体基板のおもて面において、エミッタ領域の境界の少なくとも一部が曲線形状である半導体装置を提供する。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)
Also published as:
CN107636835JPWO2017099095