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1. (WO2017099024) ACTIVE MATRIX SUBSTRATE AND LIQUID CRYSTAL DISPLAY PANEL PROVIDED WITH SAME
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/099024 International Application No.: PCT/JP2016/085949
Publication Date: 15.06.2017 International Filing Date: 02.12.2016
IPC:
H01L 29/786 (2006.01) ,G02F 1/1368 (2006.01) ,G09F 9/30 (2006.01) ,H01L 21/28 (2006.01) ,H01L 21/336 (2006.01) ,H01L 29/41 (2006.01) ,H01L 29/417 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
G PHYSICS
02
OPTICS
F
DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
1
Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
01
for the control of the intensity, phase, polarisation or colour
13
based on liquid crystals, e.g. single liquid crystal display cells
133
Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
136
Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
1362
Active matrix addressed cells
1368
in which the switching element is a three-electrode device
G PHYSICS
09
EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
F
DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
9
Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
30
in which the desired character or characters are formed by combining individual elements
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
28
Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/268158
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40
Electrodes
41
characterised by their shape, relative sizes or dispositions
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40
Electrodes
41
characterised by their shape, relative sizes or dispositions
417
carrying the current to be rectified, amplified or switched
Applicants:
シャープ株式会社 SHARP KABUSHIKI KAISHA [JP/JP]; 大阪府堺市堺区匠町1番地 1, Takumi-cho, Sakai-ku, Sakai City, Osaka 5908522, JP
Inventors:
冨田 雅裕 TOMIDA Masahiro; --
織田 明博 ODA Akihiro; --
Agent:
奥田 誠司 OKUDA Seiji; JP
Priority Data:
2015-24021409.12.2015JP
Title (EN) ACTIVE MATRIX SUBSTRATE AND LIQUID CRYSTAL DISPLAY PANEL PROVIDED WITH SAME
(FR) SUBSTRAT À MATRICE ACTIVE ET PANNEAU D'AFFICHAGE À CRISTAUX LIQUIDES MUNI DE CELUI-CI
(JA) アクティブマトリクス基板およびそれを備える液晶表示パネル
Abstract:
(EN) A plurality of TFTs, which are formed in a peripheral circuit region of an active matrix substrate according to one embodiment of the present invention, include a TFT (10A) wherein, when viewed from the direction perpendicular to a substrate (11A): the length (WAos) of an oxide semiconductor layer (14A) in the channel width direction is shorter than the length (WAg) of a gate electrode (12A) in the channel width direction; the length (WAs) of a source electrode region (15AR) in the channel width direction, in said source electrode region (15AR) a source electrode (15A) being in contact with the oxide semiconductor layer (14A), is shorter than the length (WAos) of the oxide semiconductor layer (14A) in the channel width direction; a drain electrode (16A) is in contact with the oxide semiconductor layer (14A) in a plurality of drain electrode regions (16AR) that are arranged in the channel width direction; and the total length (WAd) of the plurality of drain electrode regions (16AR) in the channel width direction is shorter than the length (WAos) of the oxide semiconductor layer (14A) in the channel width direction.
(FR) Selon l'invention, une pluralité de TFT, formés dans une région de circuit périphérique d'un substrat à matrice active selon un mode de réalisation de la présente invention, comprend un TFT (10A) caractérisé en ce que, vu suivant la direction perpendiculaire à un substrat (11A): la longueur (WAos) d'un couche (14A) de semi-conducteur à oxyde dans le sens de la largeur d'un canal est plus courte que la longueur (WAg) d'une électrode (12A) de grille dans le sens de la largeur du canal; la longueur (WAs) d'une région (15AR) d'électrode de source dans le sens de la largeur du canal, dans ladite région (15AR) d'électrode de source, une électrode (15A) de source étant en contact avec la couche (14A) de semi-conducteur à oxyde, est plus courte que la longueur (WAos) de la couche (14A) de semi-conducteur à oxyde dans le sens de la largeur du canal; une électrode (16A) de drain est en contact avec la couche (14A) de semi-conducteur à oxyde dans une pluralité de régions (16AR) d'électrode de drain qui sont disposées dans le sens de la largeur du canal; et la longueur totale (WAd) de la pluralité de régions (16AR) d'électrode de drain dans le sens de la largeur du canal est plus courte que la longueur (WAos) de la couche (14A) de semi-conducteur à oxyde dans le sens de la largeur du canal.
(JA) 実施形態のアクティブマトリクス基板が有する周辺回路領域に形成された複数のTFTは、基板(11A)に垂直な方向から見たとき、酸化物半導体層(14A)のチャネル幅方向の長さ(WAos)はゲート電極(12A)のチャネル幅方向の長さ(WAg)よりも小さく、ソース電極(15A)が酸化物半導体層(14A)と接触するソース電極領域(15AR)のチャネル幅方向の長さ(WAs)は酸化物半導体層(14A)のチャネル幅方向の長さ(WAos)よりも小さく、かつ、ドレイン電極(16A)は酸化物半導体層(14A)と、チャネル幅方向に配置された複数のドレイン電極領域(16AR)で接触し、複数のドレイン電極領域(16AR)の全体のチャネル幅方向の長さ(WAd)は酸化物半導体層(14A)のチャネル幅方向の長さ(WAos)よりも小さいTFT(10A)を含む。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)
Also published as:
US20180356660