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1. (WO2017097069) SHIFT REGISTER UNIT AND DRIVING METHOD, GATE DRIVE CIRCUIT, AND DISPLAY APPARATUS
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/097069 International Application No.: PCT/CN2016/104528
Publication Date: 15.06.2017 International Filing Date: 04.11.2016
IPC:
G09G 3/20 (2006.01)
G PHYSICS
09
EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
G
ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
3
Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
20
for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
Applicants:
BOE TECHNOLOGY GROUP CO., LTD. [CN/CN]; No.10 Jiuxianqiao Rd., Chaoyang District Beijing 100015, CN
Inventors:
CHOI, Hyunsic; CN
HAN, Seungwoo; CN
Agent:
TEE&HOWE INTELLECTUAL PROPERTY ATTORNEYS; Yuan CHEN 10th Floor, Tower D, Minsheng Financial Center 28 Jianguomennei Avenue, Dongcheng District Beijing 100005, CN
Priority Data:
201510903753.809.12.2015CN
Title (EN) SHIFT REGISTER UNIT AND DRIVING METHOD, GATE DRIVE CIRCUIT, AND DISPLAY APPARATUS
(FR) UNITÉ DE REGISTRE À DÉCALAGE ET PROCÉDÉ D'ATTAQUE, CIRCUIT D'ATTAQUE DE GÂCHETTE, ET APPAREIL D'AFFICHAGE
Abstract:
(EN) An N-th shift register unit circuit (100, 300) includes at least a gate-drive signal output sub-circuit (11), a pull-up control sub-circuit (13), and a pull-down control sub-circuit (14) respectively connected between a pull-up node (PU) and a pull-down node (PD) and provided with a p-th clock signal (CLKp) in addition to an n-th clock signal (CLKn). A driving method includes controlling the pull-down node (PD) at turn-off voltage level (VGL) when the p-th clock signal (CLKp) is at turn-on voltage level during which the n-th clock signal (CLKn) is correspondingly rising to turn-on voltage level from turn-off voltage level (VGL).
(FR) L'invention concerne un n-ième circuit d'unité de registre à décalage (100, 300) comprenant au moins un circuit secondaire de délivrance de signal d'attaque de gâchette (11), un circuit secondaire de tirage au positif (13) et un circuit secondaire de tirage à la masse (14) respectivement connectés entre un nœud de tirage au positif (PU) et un nœud de tirage à la masse (PD), et recevant un p-ième signal d'horloge (CLKp) en plus d'un n-ième signal d'horloge (CLKn). Un procédé d'attaque selon l'invention comprend la commande du nœud de tirage à la masse (PD) au niveau de tension de coupure (VGL) lorsque le p-ième signal d'horloge (CLKp) se trouve au niveau de tension d'activation pendant lequel le n-ième signal d'horloge (CLKn) se trouve en croissance correspondante vers le niveau de tension d'activation depuis le niveau de tension de coupure (VGL).
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
US20170365204