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1. (WO2017097046) SHIFT REGISTER, GATE DRIVING CIRCUIT CONTAINING THE SAME, AND METHOD FOR DRIVING THE SAME
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/097046 International Application No.: PCT/CN2016/103209
Publication Date: 15.06.2017 International Filing Date: 25.10.2016
IPC:
G09G 3/36 (2006.01) ,G11C 19/28 (2006.01)
G PHYSICS
09
EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
G
ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
3
Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
20
for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
34
by control of light from an independent source
36
using liquid crystals
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
19
Digital stores in which the information is moved stepwise, e.g. shift registers
28
using semiconductor elements
Applicants:
BOE TECHNOLOGY GROUP CO., LTD. [CN/CN]; No.10 Jiuxianqiao Rd., Chaoyang District Beijing 100015, CN
Inventors:
SUN, Tuo; CN
MA, Zhanjie; CN
Agent:
TEE&HOWE INTELLECTUAL PROPERTY ATTORNEYS; Yuan Chen, 10th Floor, Tower D Minsheng Financial Center 28 Jianguomennei Avenue Dongcheng District, Beijing 100005, CN
Priority Data:
201510907055.509.12.2015CN
Title (EN) SHIFT REGISTER, GATE DRIVING CIRCUIT CONTAINING THE SAME, AND METHOD FOR DRIVING THE SAME
(FR) REGISTRE À DÉCALAGE, CIRCUIT DE PILOTAGE DE GRILLE LE CONTENANT, ET SON PROCÉDÉ DE PILOTAGE
Abstract:
(EN) A shift register includes: an input circuit (101), electrically connected to a triggering signal line that provides a triggering signal (STV), a first clock signal line that provides a first clock signal (CK1), and a first node (A); configured for controlling whether the triggering signal (STV) is outputted to the first node (A) based on the first clock signal (CK1);a control circuit (102) electrically connected to the first node (A), a second node (B), the first clock signal line, a second clock signal line that provides a second clock signal (CK2), and a turn-on signal line that provides a turn-on signal (VP), configured for controlling whether the turn-on signal (VP) is outputted to the second node (B); and an output circuit (103), electrically connected to the first node (A), the second node (B), a first signal line that provides a first signal, a second signal line that provides a second signal, and a driving signal output line that outputs a driving signal (OUT).
(FR) L'invention concerne un registre à décalage qui comprend : un circuit d'entrée (101), connecté électriquement à une ligne de signal de déclenchement qui fournit un signal de déclenchement (STV), une ligne de premier signal d'horloge qui fournit un premier signal d'horloge (CK1), et un premier nœud (A); configuré pour commander le point de savoir si le signal de déclenchement (STV) est délivré au premier nœud (A) sur la base du premier signal d'horloge (CK1); un circuit de commande (102) connecté électriquement au premier nœud (A), à un second nœud (B), à la ligne de premier signal d'horloge, à une ligne de second signal d'horloge qui fournit un second signal d'horloge (CK2), et à une ligne de signal de mise sous tension qui fournit un signal de mise sous tension (VP), configuré pour commander le point de savoir si le signal de mise sous tension (VP) est délivré au second nœud (B); et un circuit de sortie (103), connecté électriquement au premier nœud (A), au second nœud (B), à une ligne de premier signal qui fournit un premier signal, à une ligne de second signal qui fournit un second signal, et à une ligne de délivrance de signal de pilotage qui délivre un signal de pilotage (OUT).
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
US20170330633EP3387644