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1. (WO2017096038) SYSTEMS AND METHODS OF TESTING MULTIPLE DIES
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/096038 International Application No.: PCT/US2016/064412
Publication Date: 08.06.2017 International Filing Date: 01.12.2016
IPC:
G01R 31/28 (2006.01) ,H01L 21/301 (2006.01)
G PHYSICS
01
MEASURING; TESTING
R
MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31
Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
28
Testing of electronic circuits, e.g. by signal tracer
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
301
to subdivide a semiconductor body into separate parts, e.g. making partitions
Applicants:
TEXAS INSTRUMENTS INCORPORATED [US/US]; P.O. Box 655474, Mail Station 3999 Dallas, TX 75265-5474, US
TEXAS INSTRUMENTS JAPAN LIMITED [JP/JP]; 24-1, Nishi-Shinjuku 6-chome Shinjuku-ku Tokyo, 160-8366, JP (JP)
Inventors:
PAREKHJI, Rubin Ajit; IN
MEHENDALE, Mahesh M.; IN
MENEZES, Vinod; IN
SINGHAL, Vipul K.; IN
Agent:
DAVIS, Jr., Michael A.; US
Priority Data:
15/130,42915.04.2016US
6457/CHE/201501.12.2015IN
Title (EN) SYSTEMS AND METHODS OF TESTING MULTIPLE DIES
(FR) SYSTÈMES ET PROCÉDÉS D'ESSAI DE MULTIPLES PUCES
Abstract:
(EN) In described examples of a method (800) of testing a semiconductor wafer including a scribe line and multiple dies, the method (800) includes implementing a first landing pad on the scribe line (802), and implementing a first interconnect on the scribe line and between the first landing pad and a first cluster of the plurality of dies (804), thereby coupling the first landing pad to the first cluster of dies. The method (800) further includes performing the testing of the first cluster of dies using automated test equipment (ATE) coupled to a probe tip by contacting the first landing pad with the probe tip and applying an ATE resource to the first cluster of dies (806).
(FR) Selon l'invention, dans des exemples décrits d'un procédé (800) d'essai d'une tranche de semi-conducteur comprenant une ligne de séparation et de multiples puces, le procédé (800) consiste à mettre en œuvre un premier tampon de butée sur la ligne de séparation (802) et mettre en œuvre un premier interconnecteur sur la ligne de séparation et entre le premier tampon de butée et un premier groupe de la pluralité de puces (804), couplant ainsi le premier tampon de butée au premier groupe de puces. Le procédé (800) consiste en outre à effectuer l'essai du premier groupe de puces à l'aide d'un équipement d'essai automatisé (ATE) couplé à une pointe de sonde par la mise en contact du premier tampon de butée avec la pointe de sonde et l'application d'une ressource ATE sur le premier groupe de puces (806).
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
CN108351378