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1. (WO2017095548) INTEGRATED CIRCUIT WITH CHIP-ON-CHIP AND CHIP-ON-SUBSTRATE CONFIGURATION
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Claims

What is claimed is:

1. An integrated circuit, comprising:

an optical transceiver having an opto-electronic component disposed in a first portion of a die, proximate to a surface of the die; and

at least a trace coupled with the opto-electronic component and disposed proximate to the surface of the die to extend substantially to the surface in a second portion of the die adj acent to the first portion, to provide electrical connection for the integrated circuit and another integrated circuit to be coupled with the second portion of the die in a chip-on-chip configuration.

2. The integrated circuit of claim 1, wherein the integrated circuit is a first integrated circuit, wherein the other integrated circuit is a second integrated circuit, wherein at least a trace comprises at least a first trace, and wherein the first integrated circuit further comprises at least a second trace disposed proximate to the surface in the second portion of the die to extend substantially to the surface in the second portion, to provide electrical connection for the second integrated circuit and a substrate to be coupled with the second portion of the die in a chip-on-substrate configuration.

3. The integrated circuit of claim 2, wherein the second integrated circuit is to be disposed on the second portion of the die in the chip-on-chip configuration with the first integrated circuit.

4. The integrated circuit of claim 2, wherein the substrate is to be disposed over the second portion of the die in the chip-on-substrate configuration with the second integrated circuit.

5. The integrated circuit of claim 2, wherein the opto-electronic component comprises a normal-incidence photodetector (NIPD), to receive an optical signal and transmit a corresponding electrical output signal via the at least a first trace, wherein the second integrated circuit comprises a receiver, to amplify the electrical output signal and to provide the amplified electrical output signal to circuitry disposed in the substrate via the at least a second trace.

6. The integrated circuit of claim 5, further comprising an array of lenses optically coupled with the NIPD, wherein the at least a first trace comprises a first plurality of traces, to electrically couple the NIPD with inputs of the receiver.

7. The integrated circuit of claim 6, wherein the at least a second trace comprises a second plurality of traces, to electrically couple outputs of the receiver with the circuitry disposed in the substrate.

8. The integrated circuit of claim 7, wherein the second plurality of traces are disposed in the second portion of the die in a multi-layered fashion.

9. The integrated circuit of claim 7, wherein the first and second plurality of traces include contact pads disposed at respective ends of traces to extend to the surface of the die, to provide electrical connectivity for the first and second integrated circuits and the circuitry disposed in the substrate.

10. The integrated circuit of claim 6, wherein the array of lenses is disposed above the first portion of the die, wherein each of the lenses includes a facet, to prevent formation of resonant cavities between the lenses and the NIPD.

11. The integrated circuit of claim 10, wherein the die includes a distributed Bragg reflector multilayer stack, to provide a determined optical response for the NIPD.

12. The integrated circuit of claim 7, wherein the surface is a first surface, wherein the die includes a semiconductor substrate having a second surface opposite the first surface, wherein the array of lenses is disposed on the second surface in the first portion of the die.

13. The integrated circuit of claim 12, wherein at least one of the second plurality of traces comprises a reflector, to provide a determined optical response for the NIPD.

14. The integrated circuit of any of claims 2 to 13, wherein the substrate comprises a printed circuit board (PCB).

15. An apparatus with a chip-on-chip and chip-on-substrate configuration, comprising:

a processor; and

an optical transceiver communicatively coupled with the processor, and including an opto-electronic component disposed in a first portion of a die, proximate to a surface of the die; and

at least a trace coupled with the opto-electronic component and disposed proximate to the surface of the die to extend substantially to the surface in a second portion of the die adjacent to the first portion, to provide electrical connection for the optical transceiver and an integrated circuit to be coupled with the second portion of the die in a chip-on-chip

configuration, to provide communicative connection between the apparatus and another apparatus.

16. The apparatus of claim 15, wherein the optical transceiver is a first integrated circuit and wherein the integrated circuit is a second integrated circuit, wherein the at least trace is at least a first trace, wherein the first integrated circuit further comprises at least a second trace disposed proximate to the surface in the second portion of the die to extend substantially to the surface in the second portion, to provide electrical connection for the second integrated circuit and a substrate to be coupled with the second portion of the die in a chip-on-substrate configuration.

17. The apparatus of claim 16, wherein the second integrated circuit is to be disposed on the second portion of the die in the chip-on-chip configuration with the first integrated circuit, wherein the substrate is to be disposed over the second portion of the die in the chip-on-substrate configuration with the second integrated circuit.

18. The apparatus of claim 17, wherein the substrate comprises a printed circuit board (PCB), wherein the apparatus comprises a mobile computing device.

19. A method for providing an integrated circuit, comprising:

disposing an opto-electronic component of an optical transceiver in a first portion of a die, proximate to a surface of the die;

disposing at least a trace proximate to the surface of the die, including extending the at least a trace substantially to the surface in a second portion of the die adjacent to the first portion; and

coupling the opto-electronic component with the at least a trace, to provide electrical connection for the optical transceiver and an integrated circuit to be coupled with the second portion of the die in a chip-on-chip configuration.

20. The method of claim 19, wherein the optical transceiver comprises a first integrated circuit disposed in the die and wherein the integrated circuit is a second integrated circuit, wherein the at least trace is at least a first trace, wherein the method further comprises:

disposing at least a second trace proximate to the surface in the second portion of the die, including extending the at least a second trace substantially to the surface in the second portion, to provide electrical connection for the second integrated circuit and a substrate to be coupled with the second portion of the die in a chip-on-substrate configuration.

21. The method of claim 20, wherein the opto-electronic component comprises a normal-incidence photodetector (NIPD), wherein the second integrated circuit comprises a receiver, wherein the method further comprises:

disposing an array of lenses on the die, to provide optical coupling for a light source coupled with the first integrated circuit, with the NIPD.

22. The method of claim 21 , wherein disposing an array of lenses on the die includes providing the array of lenses above the first portion of the die.

23. The method of claim 21 , wherein the surface is a first surface, wherein the die includes a dielectric substrate having a second surface opposite the first surface, wherein the disposing an array of lenses on the die includes providing the array of lenses on the second surface in the first portion of the die.

24. The method of claim 20, further comprising:

disposing the second integrated circuit on the second portion of the die in the chip-on-chip configuration.

25. The method of any of claims 20 to 24, further comprising:

disposing the substrate over the second portion of the die in the chip-on-substrate configuration.