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1. (WO2017095548) INTEGRATED CIRCUIT WITH CHIP-ON-CHIP AND CHIP-ON-SUBSTRATE CONFIGURATION
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/095548 International Application No.: PCT/US2016/058068
Publication Date: 08.06.2017 International Filing Date: 21.10.2016
IPC:
H01L 25/16 (2006.01) ,H01L 25/065 (2006.01) ,H01L 25/11 (2006.01) ,H01L 25/00 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
16
the devices being of types provided for in two or more different main groups of groups H01L27/-H01L51/139
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
065
the devices being of a type provided for in group H01L27/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
10
the devices having separate containers
11
the devices being of a type provided for in group H01L29/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors:
DOSUNMU, Olufemi I.; US
YIM, Myung Jin; US
LIU, Ansheng; US
Agent:
RASKIN, Vladimir; US
AUYEUNG, Al; US
BLAIR, Steven R.; US
COFIELD, Michael A.; US
COWGER, Graciela G.; US
DANSKIN, Timothy A.; US
FORD, Stephen S.; US
GARTHWAITE, Martin S.; US
LEE, Katherine D.; US
MAKI, Nathan R.; US
MARLINK, Jeffrey S.; US
MEININGER, Mark M.; US
MOORE, Michael S.; US
PARKER, Wesley E.; US
STRAUSS, Ryan N.; US
WANG, Yuke; US
Priority Data:
14/956,19101.12.2015US
Title (EN) INTEGRATED CIRCUIT WITH CHIP-ON-CHIP AND CHIP-ON-SUBSTRATE CONFIGURATION
(FR) CIRCUIT INTÉGRÉ À CONFIGURATION PUCE-SUR-PUCE ET PUCE-SUR-SUBSTRAT
Abstract:
(EN) Embodiments of the present disclosure provide an apparatus comprising an integrated circuit with a chip-on-chip and chip-on-substrate configuration. In one instance, apparatus may include optical transceiver with opto-electronic component disposed in a first portion of a die, and a trace coupled with opto-electronic component and disposed to extend substantially to a surface in a second portion of the die adjacent to first portion, to provide electrical connection for the integrated circuit and another integrated circuit to be coupled with second portion of the die in chip-on-chip configuration. The apparatus may include a second trace disposed in second portion of the die to extend substantially to surface in second portion, to provide electrical connection for other integrated circuit and a substrate to be coupled with second portion of the die in chip-on-substrate configuration. Other embodiments may be described and/or claimed.
(FR) La présente invention concerne, dans ses modes de réalisation, un appareil qui comprend un circuit intégré à configuration puce-sur-puce et puce-sur-substrat. Dans un exemple, l'appareil peut comprendre un émetteur-récepteur optique à composant optoélectronique disposé dans une première partie d'un dé, et une trace couplée au composant optoélectronique et disposée pour s'étendre sensiblement sur une surface dans une seconde partie du dé adjacente à la première partie, pour fournir une connexion électrique pour le circuit intégré et un autre circuit intégré destiné à être couplé à la seconde partie du dé en configuration puce-sur-puce. L'appareil peut comprendre une seconde trace disposée dans la seconde partie du dé pour s'étendre sensiblement jusqu'à la surface dans la seconde partie, pour fournir une connexion électrique pour un autre circuit intégré et un substrat destiné à être couplé à la seconde partie du dé en configuration puce-sur-substrat. D'autres modes de réalisation peuvent être décrits et/ou revendiqués.
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
CN108369945DE112016005492